diff options
| author | Sam Lewis <sam.vr.lewis@gmail.com> | 2020-08-06 21:13:22 +1000 |
|---|---|---|
| committer | Arthur Heymans <arthur@aheymans.xyz> | 2021-03-30 11:21:49 +0000 |
| commit | 7cbf391bce785cf3a815dc6a841f80611b4db6fe (patch) | |
| tree | d481ad50ffedbbccc7e051c092849cb760509d9c /src/mainboard/ti/beaglebone/Kconfig | |
| parent | 1d8d99bfd93602bbcc4f318f384a93cdad045705 (diff) | |
| download | coreboot-7cbf391bce785cf3a815dc6a841f80611b4db6fe.tar.xz | |
mb/ti/beaglebone: Initialize DDR3
Adds initialisation of 512MB of DDR memory on the BBB to the romstage.
The parameters for the DDR peripherals are taken from U-Boot.
TEST: Booted from romstage into ramstage. Also successfully managed to
run the "ram_check" in lib.h.
Change-Id: I692bfd913c8217a78d073d19c5344c9bb40722a8
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Diffstat (limited to 'src/mainboard/ti/beaglebone/Kconfig')
| -rw-r--r-- | src/mainboard/ti/beaglebone/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index ab3d38189f..7881bdf1ae 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -24,7 +24,7 @@ config MAX_CPUS config DRAM_SIZE_MB int - default 256 + default 512 config UART_FOR_CONSOLE int |