summaryrefslogtreecommitdiff
path: root/src/mainboard/ti/beaglebone
diff options
context:
space:
mode:
authorHung-Te Lin <hungte@chromium.org>2013-06-11 21:55:58 -0700
committerStefan Reinauer <stefan.reinauer@coreboot.org>2013-07-10 21:46:01 +0200
commitd63bddc4991d9ace037fd716b29c3f7253e9ac94 (patch)
tree73903c59bb20a3e28e7b11eb59097df0459588c6 /src/mainboard/ti/beaglebone
parent32ab283b1086ef53fadcd4be92df6e41c5d06438 (diff)
downloadcoreboot-d63bddc4991d9ace037fd716b29c3f7253e9ac94.tar.xz
armv7: Reserve space BL1 and checksum header by specifying bootblock offset.
Not all ARM systems need "BL1", and the layout of BL* and bootblock may be different (ex, Exynos 5250 may use a new BL1 with variable length checksum header). To support that better, define the real base address (and ROM offset) of boot block, and then we can post-processing ROM image file by filling data / checksum and any other information. Change-Id: I0e3105e52500b6b457371ad33a9aa546acf28928 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/3664 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/ti/beaglebone')
-rw-r--r--src/mainboard/ti/beaglebone/Kconfig12
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig
index 1cde042f43..8651c9bf4b 100644
--- a/src/mainboard/ti/beaglebone/Kconfig
+++ b/src/mainboard/ti/beaglebone/Kconfig
@@ -54,6 +54,18 @@ config NR_DRAM_BANKS
int
default 1
+config BOOTBLOCK_ROM_OFFSET
+ hex
+ default 0x0
+
+config CBFS_HEADER_ROM_OFFSET
+ hex
+ default 0x10
+
+config CBFS_ROM_OFFSET
+ hex
+ default 0x5000
+
choice CONSOLE_SERIAL_UART_CHOICES
prompt "Serial Console UART"
default CONSOLE_SERIAL_UART0