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authorRizwan Qureshi <rizwan.qureshi@intel.com>2017-09-05 14:18:25 +0530
committerAaron Durbin <adurbin@chromium.org>2017-09-06 16:39:58 +0000
commit6ab4ed40d355a55f0ff8e8aade55be796a256c0d (patch)
tree94099a66ca3f6172e5ecfbab60acc77b70de194c /src/mainboard/ti
parent33f1273f9f1e41c1c7f42732dd9430e40476abc3 (diff)
downloadcoreboot-6ab4ed40d355a55f0ff8e8aade55be796a256c0d.tar.xz
soc/intel/skylake: Add config for enabling PCIe AER
Add a config for enabling/disabling Advanced Error Reporting feature for PCIe root ports. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: Ieb74c3566ded2276e549c98f78813c4f5d4d310a Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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