- First pass at getting the powerpc ports to compile

  The static device tree is not built properly at all yet, but at least we get through it.
  FIXME (What is the proper way to handle add in boards?)
- Add generic div64 support and ppc div64 support
- Fix abuild so it properly generates the CC line when cross compiling.
- Add one more possible ppc cross compiler target


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 84 insertions, 4 deletions

diff --git a/src/mainboard/totalimpact/briq/Config.lb b/src/mainboard/totalimpact/briq/Config.lb
index 943018d025..775aad36f8 100644
--- a/src/mainboard/totalimpact/briq/Config.lb
+++ b/src/mainboard/totalimpact/briq/Config.lb
@@ -16,17 +16,17 @@ object clock.o
 arch ppc end
 
 if CONFIG_BRIQ_750FX
-	cpu ppc/ppc7xx end
+	chip cpu/ppc/ppc7xx device pnp 0.0 on end end
 end
 if CONFIG_BRIQ_7400
-	cpu ppc/mpc74xx end
+	chip cpu/ppc/mpc74xx device pnp 0.0 on end  end
 end
 
 ##
 ## Include the secondary Configuration files 
 ##
-northbridge ibm/cpc710 end
-southbridge winbond/w83c553 end
+chip northbridge/ibm/cpc710 device pnp 0.0 on end end
+chip southbridge/winbond/w83c553 device pnp 0.0 on end end
 
 ##
 ## Build the objects we have code for in this directory.
diff --git a/src/mainboard/totalimpact/briq/Options.lb b/src/mainboard/totalimpact/briq/Options.lb
index 37bfa24c72..557290f8ff 100644
--- a/src/mainboard/totalimpact/briq/Options.lb
+++ b/src/mainboard/totalimpact/briq/Options.lb
@@ -11,6 +11,32 @@ uses ISA_MEM_BASE
 uses PCIC0_CFGADDR
 uses PCIC0_CFGDATA
 uses _IO_BASE
+uses CROSS_COMPILE 
+uses HAVE_OPTION_TABLE
+uses CONFIG_COMPRESS 
+uses DEFAULT_CONSOLE_LOGLEVEL 
+uses CONFIG_USE_INIT
+uses NO_POST
+uses CONFIG_CONSOLE_SERIAL8250 
+uses CONFIG_IDE_STREAM 
+uses IDE_BOOT_DRIVE
+uses IDE_SWAB IDE_OFFSET 
+uses ROM_SIZE
+uses _RESET
+uses _EXCEPTION_VECTORS
+uses _ROMBASE
+uses _ROMSTART
+uses _RAMBASE
+uses _RAMSTART
+uses STACK_SIZE
+uses HEAP_SIZE
+uses CONFIG_BRIQ_750FX 
+uses CONFIG_BRIQ_7400
+
+uses MAINBOARD
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PART_NUMBER
+uses LINUXBIOS_EXTRA_VERSION
 uses CROSS_COMPILE
 uses CC
 uses HOSTCC
@@ -33,3 +59,57 @@ default TTYS0_DIV=4
 ## Set UART base address
 ##
 default TTYS0_BASE=0x3f8
+
+## use a cross compiler
+#default CROSS_COMPILE="powerpc-eabi-"
+#default CROSS_COMPILE="ppc_74xx-"
+
+## Use stage 1 initialization code
+default CONFIG_USE_INIT=1
+
+## We don't use compressed image
+default CONFIG_COMPRESS=0
+
+## Turn off POST codes
+default NO_POST=1
+
+## Enable serial console
+default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Boot linux from IDE
+default CONFIG_IDE_STREAM=1
+default IDE_BOOT_DRIVE=0
+default IDE_SWAB=1
+default IDE_OFFSET=0
+
+# ROM is 1Mb
+default ROM_SIZE=1048576
+
+# Set stack and heap sizes (stage 2)
+default STACK_SIZE=0x10000
+default HEAP_SIZE=0x10000
+
+# Sandpoint Demo Board
+## Base of ROM
+default _ROMBASE=0xfff00000
+
+## Sandpoint reset vector
+default _RESET=_ROMBASE+0x100
+
+## Exception vectors (other than reset vector)
+default _EXCEPTION_VECTORS=_RESET+0x100
+
+## Start of linuxBIOS in the boot rom
+## = _RESET + exeception vector table size
+default _ROMSTART=_RESET+0x3100
+
+## LinuxBIOS C code runs at this location in RAM
+default _RAMBASE=0x00100000
+default _RAMSTART=0x00100000
+
+default CONFIG_BRIQ_750FX=1
+#default CONFIG_BRIQ_7400=1
+
+### End Options.lb
+end