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authorEric Biederman <ebiederm@xmission.com>2004-11-05 10:48:04 +0000
committerEric Biederman <ebiederm@xmission.com>2004-11-05 10:48:04 +0000
commit709850a21b1bdfb0018aa2a7ee06a7407bbd465c (patch)
tree9aa0549858c03180139a7d528e5cb21982eff1ba /src/mainboard/totalimpact
parentd0805e0b55e63957b3641fa70cf1db624389e3f6 (diff)
downloadcoreboot-709850a21b1bdfb0018aa2a7ee06a7407bbd465c.tar.xz
- Ensure every copy of Options.lb uses:
CROSS_COMPILE CC HOSTCC OBJCOPY git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/totalimpact')
-rw-r--r--src/mainboard/totalimpact/briq/Config.lb28
-rw-r--r--src/mainboard/totalimpact/briq/Options.lb35
2 files changed, 35 insertions, 28 deletions
diff --git a/src/mainboard/totalimpact/briq/Config.lb b/src/mainboard/totalimpact/briq/Config.lb
index 6c54d85120..943018d025 100644
--- a/src/mainboard/totalimpact/briq/Config.lb
+++ b/src/mainboard/totalimpact/briq/Config.lb
@@ -2,34 +2,6 @@
## Config file for the Total Impact briQ
##
-uses TTYS0_DIV
-uses TTYS0_BASE
-uses CONFIG_BRIQ_750FX
-uses CONFIG_BRIQ_7400
-uses ISA_IO_BASE
-uses ISA_MEM_BASE
-uses PCIC0_CFGADDR
-uses PCIC0_CFGDATA
-uses _IO_BASE
-
-##
-## Set memory map
-##
-default ISA_IO_BASE=0x80000000
-default ISA_MEM_BASE=0xc0000000
-default PCIC0_CFGADDR=0xff5f8000
-default PCIC0_CFGDATA=0xff5f8010
-default _IO_BASE=ISA_IO_BASE
-
-##
-## The briQ uses weird clocking, 4 = 115200
-##
-default TTYS0_DIV=4
-##
-## Set UART base address
-##
-default TTYS0_BASE=0x3f8
-
##
## Early board initialization, called from ppc_main()
##
diff --git a/src/mainboard/totalimpact/briq/Options.lb b/src/mainboard/totalimpact/briq/Options.lb
new file mode 100644
index 0000000000..37bfa24c72
--- /dev/null
+++ b/src/mainboard/totalimpact/briq/Options.lb
@@ -0,0 +1,35 @@
+##
+## Config file for the Total Impact briQ
+##
+
+uses TTYS0_DIV
+uses TTYS0_BASE
+uses CONFIG_BRIQ_750FX
+uses CONFIG_BRIQ_7400
+uses ISA_IO_BASE
+uses ISA_MEM_BASE
+uses PCIC0_CFGADDR
+uses PCIC0_CFGDATA
+uses _IO_BASE
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+
+##
+## Set memory map
+##
+default ISA_IO_BASE=0x80000000
+default ISA_MEM_BASE=0xc0000000
+default PCIC0_CFGADDR=0xff5f8000
+default PCIC0_CFGDATA=0xff5f8010
+default _IO_BASE=ISA_IO_BASE
+
+##
+## The briQ uses weird clocking, 4 = 115200
+##
+default TTYS0_DIV=4
+##
+## Set UART base address
+##
+default TTYS0_BASE=0x3f8