amd/geode_lx: Remove most boards

There is active work to convert remaining two boards,
PC Engines alix1c and alix2d, to EARLY_CBMEM_INIT.

Change-Id: I87e3963af7ef719e9fa2a8b0df34a896265905f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed, 0 insertions, 263 deletions

diff --git a/src/mainboard/traverse/Kconfig b/src/mainboard/traverse/Kconfig
deleted file mode 100644
index 7dec5e1d70..0000000000
--- a/src/mainboard/traverse/Kconfig
+++ /dev/null
@@ -1,16 +0,0 @@
-if VENDOR_TRAVERSE
-
-choice
-	prompt "Mainboard model"
-
-source "src/mainboard/traverse/*/Kconfig.name"
-
-endchoice
-
-source "src/mainboard/traverse/*/Kconfig"
-
-config MAINBOARD_VENDOR
-	string
-	default "Traverse Technologies"
-
-endif # VENDOR_TRAVERSE
diff --git a/src/mainboard/traverse/geos/Kconfig b/src/mainboard/traverse/geos/Kconfig
deleted file mode 100644
index 354ca810b4..0000000000
--- a/src/mainboard/traverse/geos/Kconfig
+++ /dev/null
@@ -1,32 +0,0 @@
-if BOARD_TRAVERSE_GEOS
-
-config BOARD_SPECIFIC_OPTIONS # dummy
-	def_bool y
-	select CPU_AMD_GEODE_LX
-	select NORTHBRIDGE_AMD_LX
-	select SOUTHBRIDGE_AMD_CS5536
-	select HAVE_PIRQ_TABLE
-	select PIRQ_ROUTE
-	select UDELAY_TSC
-	select BOARD_ROMSIZE_KB_1024
-	select POWER_BUTTON_DEFAULT_DISABLE
-	select PLL_MANUAL_CONFIG
-	select CORE_GLIU_500_400
-
-config MAINBOARD_DIR
-	string
-	default traverse/geos
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Geos"
-
-config IRQ_SLOT_COUNT
-	int
-	default 6
-
-config PLLMSRlo
-	hex
-	default 0x00de602e
-
-endif # BOARD_TRAVERSE_GEOS
diff --git a/src/mainboard/traverse/geos/Kconfig.name b/src/mainboard/traverse/geos/Kconfig.name
deleted file mode 100644
index e446fa0b6e..0000000000
--- a/src/mainboard/traverse/geos/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_TRAVERSE_GEOS
-	bool "Geos"
diff --git a/src/mainboard/traverse/geos/board_info.txt b/src/mainboard/traverse/geos/board_info.txt
deleted file mode 100644
index 394724a9e7..0000000000
--- a/src/mainboard/traverse/geos/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Category: half
-Board URL: http://www.traverse.com.au/geos11-adsl2-x86-router-appliance
-ROM package: PLCC
-ROM socketed: y
diff --git a/src/mainboard/traverse/geos/cmos.layout b/src/mainboard/traverse/geos/cmos.layout
deleted file mode 100644
index 457d773dbb..0000000000
--- a/src/mainboard/traverse/geos/cmos.layout
+++ /dev/null
@@ -1,29 +0,0 @@
-entries
-
-0          384       r       0        reserved_memory
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#392          3       r       0        unused
-400          1       e       1        power_on_after_fail
-412          4       e       6        debug_level
-440          1       e       0        dcon_present
-456          1       e       1        ECC_memory
-1008         16      h       0        check_sum
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-
-checksums
-
-checksum 392 1007 1008
diff --git a/src/mainboard/traverse/geos/devicetree.cb b/src/mainboard/traverse/geos/devicetree.cb
deleted file mode 100644
index 4a2674e885..0000000000
--- a/src/mainboard/traverse/geos/devicetree.cb
+++ /dev/null
@@ -1,40 +0,0 @@
-chip northbridge/amd/lx
-	device domain 0 on
-		device pci 1.0 on end	# Northbridge
-		device pci 1.1 on end	# Graphics
-		chip southbridge/amd/cs5536
-			# IRQ 12 and 1 unmasked,  Keyboard and Mouse IRQs. OK
-			# SIRQ Mode = Active(Quiet) mode. Save power....
-			# Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse IRQs. OK
-			register "lpc_serirq_enable" = "0x00001002"
-			register "lpc_serirq_polarity" = "0x0000EFFD"
-			register "lpc_serirq_mode" = "1"
-			register "enable_gpio_int_route" = "0x0D0C0700"
-			register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
-			register "enable_USBP4_device" = "0"	#0: host, 1:device
-			register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
-			register "com1_enable" = "1"
-			register "com1_address" = "0x3F8"
-			register "com1_irq" = "4"
-			register "com2_enable" = "0"
-			register "com2_address" = "0x2F8"
-			register "com2_irq" = "3"
-			register "unwanted_vpci[0]" = "0"	# End of list has a zero
-			device pci a.0 on end	# Ethernet 0
-			device pci b.0 on end	# Ethernet 1
-			device pci c.0 on end	# Xilinx
-			device pci d.0 on end	# Mini PCI
-			device pci f.0 on end	# ISA Bridge
-			device pci f.2 on end	# IDE Controller
-			device pci f.3 on end	# Audio
-			device pci f.4 on end	# OHCI
-			device pci f.5 on end	# EHCI
-		end
-	end
-	# APIC cluster is late CPU init.
-	device cpu_cluster 0 on
-		chip cpu/amd/geode_lx
-			device lapic 0 on end
-		end
-	end
-end
diff --git a/src/mainboard/traverse/geos/irq_tables.c b/src/mainboard/traverse/geos/irq_tables.c
deleted file mode 100644
index 3e2e1d99a1..0000000000
--- a/src/mainboard/traverse/geos/irq_tables.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/pirq_routing.h>
-#include <console/console.h>
-#include <arch/io.h>
-#include <arch/pirq_routing.h>
-#include "southbridge/amd/cs5536/cs5536.h"
-
-/* Platform IRQs */
-#define PIRQA 11
-#define PIRQB 10
-#define PIRQC 11
-#define PIRQD 9
-
-/* Map */
-#define M_PIRQA (1 << PIRQA)	/* Bitmap of supported IRQs */
-#define M_PIRQB (1 << PIRQB)	/* Bitmap of supported IRQs */
-#define M_PIRQC (1 << PIRQC)	/* Bitmap of supported IRQs */
-#define M_PIRQD (1 << PIRQD)	/* Bitmap of supported IRQs */
-
-/* Link */
-#define L_PIRQA	 1		/* Means Slot INTx# Connects To Chipset INTA# */
-#define L_PIRQB	 2		/* Means Slot INTx# Connects To Chipset INTB# */
-#define L_PIRQC	 3		/* Means Slot INTx# Connects To Chipset INTC# */
-#define L_PIRQD	 4		/* Means Slot INTx# Connects To Chipset INTD# */
-
-static const struct irq_routing_table intel_irq_routing_table = {
-	PIRQ_SIGNATURE,		/* u32 signature */
-	PIRQ_VERSION,		/* u16 version   */
-	32 + 16 * CONFIG_IRQ_SLOT_COUNT,	/* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
-	0x00,			/* Where the interrupt router lies (bus) */
-	(0x0F << 3) | 0x0,	/* Where the interrupt router lies (dev) */
-	0x00,			/* IRQs devoted exclusively to PCI usage */
-	0x100B,			/* Vendor */
-	0x002B,			/* Device */
-	0,			/* Miniport data */
-	{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},	/* u8 rfu[11] */
-	0x00,			/*      u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
-	{
-	 /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */
-	 /* bus, dev|fn,           {link, bitmap},      {link, bitmap},     {link, bitmap},     {link, bitmap},     slot, rfu */
-	 {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0},	/* CPU */
-	 {0x00, (0x0A << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth0 */
-	 {0x00, (0x0B << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* eth1 */
-	 {0x00, (0x0C << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x2, 0x0}, /* xilinx */
-	 {0x00, (0x0D << 3) | 0x0, {{L_PIRQD, M_PIRQD}, {L_PIRQC, M_PIRQC}, {0x00, 0x00}, {0x00, 0x00}}, 0x1, 0x0}, /* mini PCI */
-	 {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0},	/* chipset */
-	}
-};
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-	return copy_pirq_routing_table(addr, &intel_irq_routing_table);
-}
diff --git a/src/mainboard/traverse/geos/romstage.c b/src/mainboard/traverse/geos/romstage.c
deleted file mode 100644
index 1dba4a3716..0000000000
--- a/src/mainboard/traverse/geos/romstage.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007 Advanced Micro Devices, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <stdlib.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <console/console.h>
-#include <lib.h>
-#include <cpu/x86/bist.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/lxdef.h>
-#include <southbridge/amd/cs5536/cs5536.h>
-#include <spd.h>
-#include <northbridge/amd/lx/raminit.h>
-
-int spd_read_byte(unsigned int device, unsigned int address)
-{
-	return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/lx/pll_reset.c"
-#include "cpu/amd/geode_lx/cpureginit.c"
-#include "cpu/amd/geode_lx/syspreinit.c"
-#include "cpu/amd/geode_lx/msrinit.c"
-
-void asmlinkage mainboard_romstage_entry(unsigned long bist)
-{
-	static const struct mem_controller memctrl[] = {
-		{.channel0 = {DIMM0, DIMM1}}
-	};
-
-	SystemPreInit();
-	msr_init();
-
-	cs5536_early_setup();
-
-	/* Note: must do this AFTER the early_setup! It is counting on some
-	 * early MSR setup for CS5536.
-	 */
-	/* cs5536_disable_internal_uart: disable them for now, set them
-	 * up later...
-	 */
-	/* If debug. real setup done in chipset init via devicetree.cb. */
-	cs5536_setup_onchipuart(1);
-	console_init();
-
-	/* Halt if there was a built in self test failure */
-	report_bist_failure(bist);
-
-	pll_reset();
-
-	cpuRegInit(0, DIMM0, DIMM1, DRAM_TERMINATED);
-
-	sdram_initialize(1, memctrl);
-
-	/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
-	return;
-}