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author | Uwe Hermann <uwe@hermann-uwe.de> | 2007-05-03 08:50:37 +0000 |
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committer | Uwe Hermann <uwe@hermann-uwe.de> | 2007-05-03 08:50:37 +0000 |
commit | d436a4b4bc035a3756a57ae8e632e16f7a95b9c9 (patch) | |
tree | e61a55cb4f885f08b52cf04a37c8d7232cdc0ead /src/mainboard/tyan/s1846/Config.lb | |
parent | 941a6f078ece125a5c116315c82fcd3cb1feaf42 (diff) | |
download | coreboot-d436a4b4bc035a3756a57ae8e632e16f7a95b9c9.tar.xz |
Correct the RAM checking code to _not_ check the range from 640 KB - 1 MB,
as that is not RAM but used for other stuff.
First try at PCI init added to src/mainboard/tyan/s1846/Config.lb.
Use a real payload (FILO) per default now.
Note: this cannot boot a payload, yet, but it gets a lot further now.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s1846/Config.lb')
-rw-r--r-- | src/mainboard/tyan/s1846/Config.lb | 37 |
1 files changed, 32 insertions, 5 deletions
diff --git a/src/mainboard/tyan/s1846/Config.lb b/src/mainboard/tyan/s1846/Config.lb index c63d895de8..7d8a3cc013 100644 --- a/src/mainboard/tyan/s1846/Config.lb +++ b/src/mainboard/tyan/s1846/Config.lb @@ -126,10 +126,37 @@ dir /pc80 config chip.h # TODO. -chip northbridge/intel/i440bx - device pci_domain 0 on - end - chip cpu/intel/slot_2 - end +chip northbridge/intel/i440bx # Northbridge + device pci_domain 0 on + device pci 0.0 on end # Host bridge + device pci 1.0 off end # PCI bridge TODO: AGP bridge? + # device pci 7.0 on end # ISA bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge ??? + chip superio/nsc/pc87309 # Super I/O + device pnp 2e.0 on end # Floppy + device pnp 2e.1 on end # Parallel port + device pnp 2e.2 on end # Com2 + device pnp 2e.3 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on end # Power mgmt. + device pnp 2e.5 on end # Mouse + device pnp 2e.6 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 # ??? + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + end + end + end + chip cpu/intel/slot_2 + end end |