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authorUwe Hermann <uwe@hermann-uwe.de>2007-04-03 10:45:53 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2007-04-03 10:45:53 +0000
commit17d667b411685de57ea181cc496b29fea6d27d91 (patch)
tree3e6a9fbc7bdb892bdde449068b12ecbaf063f851 /src/mainboard/tyan/s1846/failover.c
parent23d1e35d4d2fd25c710c5b54bfe171d8d2db0cea (diff)
downloadcoreboot-17d667b411685de57ea181cc496b29fea6d27d91.tar.xz
Add initial framework for the Tyan S1846.
It's not fully working, among other things because the Intel 440BX northbridge isn't working, yet. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s1846/failover.c')
-rw-r--r--src/mainboard/tyan/s1846/failover.c32
1 files changed, 32 insertions, 0 deletions
diff --git a/src/mainboard/tyan/s1846/failover.c b/src/mainboard/tyan/s1846/failover.c
new file mode 100644
index 0000000000..bdcb9eaed2
--- /dev/null
+++ b/src/mainboard/tyan/s1846/failover.c
@@ -0,0 +1,32 @@
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include "arch/romcc_io.h"
+#include "pc80/mc146818rtc_early.c"
+
+static unsigned long main(unsigned long bist)
+{
+ /* This is the primary cpu how should I boot? */
+ if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
+ normal_image:
+ asm volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ : /* clobbers */
+ );
+ cpu_reset:
+ asm volatile ("jmp __cpu_reset"
+ : /* outputs */
+ : "a"(bist) /* inputs */
+ : /* clobbers */
+ );
+ fallback_image:
+ return bist;
+}