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author | Yinghai Lu <yinghailu@gmail.com> | 2004-10-20 05:07:16 +0000 |
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committer | Yinghai Lu <yinghailu@gmail.com> | 2004-10-20 05:07:16 +0000 |
commit | 6a61d6a4ae26d02844bf8043525d89b0ef9e0351 (patch) | |
tree | ffe2c7e2680ccb73502fe4129b9727051792dadb /src/mainboard/tyan/s2850/auto.c | |
parent | abed01d81d0c55848232a9ebd9bb4c55d036f45d (diff) | |
download | coreboot-6a61d6a4ae26d02844bf8043525d89b0ef9e0351.tar.xz |
Tyan update to work with new CPU Config
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2850/auto.c')
-rw-r--r-- | src/mainboard/tyan/s2850/auto.c | 62 |
1 files changed, 45 insertions, 17 deletions
diff --git a/src/mainboard/tyan/s2850/auto.c b/src/mainboard/tyan/s2850/auto.c index 9d6d5b107a..bd0b43bcf3 100644 --- a/src/mainboard/tyan/s2850/auto.c +++ b/src/mainboard/tyan/s2850/auto.c @@ -4,7 +4,8 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> -#include <arch/smp/lapic.h> +#include <cpu/x86/lapic.h> +#include <arch/cpu.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" @@ -13,13 +14,15 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" -#include "cpu/k8/apic_timer.c" +#include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#include "cpu/p6/boot_cpu.c" +#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/cpu_rev.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -39,6 +42,12 @@ static void soft_reset(void) pci_write_config8(PCI_DEV(0, 0x02, 0), 0x47, 1); } +static void soft2_reset(void) +{ + set_bios_reset(); + pci_write_config8(PCI_DEV(1, 0x02, 0), 0x47, 1); +} + #define REV_B_RESET 0 static void memreset_setup(void) { @@ -102,12 +111,14 @@ static inline int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } +#include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/resourcemap.c" #include "sdram/generic_sdram.c" +#include "northbridge/amd/amdk8/resourcemap.c" -static void main(void) + +static void main(unsigned long bist) { /* * GPIO28 of 8111 will control H0_MEMRESET_L @@ -126,18 +137,35 @@ static void main(void) }; int needs_reset; - enable_lapic(); - init_timer(); - if (cpu_init_detected()) { - asm("jmp __cpu_reset"); - } - distinguish_cpu_resets(); - if (!boot_cpu()) { - stop_this_cpu(); - } - w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); - uart_init(); - console_init(); + if (bist == 0) { + /* Skip this if there was a built in self test failure */ + amd_early_mtrr_init(); + enable_lapic(); + init_timer(); + + if (cpu_init_detected()) { +#if 0 + asm volatile ("jmp __cpu_reset"); +#else + /* cpu reset also reset the memtroller ???? + need soft_reset to reset all except keep HT link freq and width */ + distinguish_cpu_resets(); + soft2_reset(); +#endif + } + distinguish_cpu_resets(); + if (!boot_cpu()) { + stop_this_cpu(); + } + } + + w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + setup_default_resource_map(); needs_reset = setup_coherent_ht_domain(); needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80); |