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| author | Li-Ta Lo <ollie@lanl.gov> | 2004-01-12 20:00:43 +0000 |
|---|---|---|
| committer | Li-Ta Lo <ollie@lanl.gov> | 2004-01-12 20:00:43 +0000 |
| commit | f0721563b48ff7e2ad1bd7398da2747ec1a3b055 (patch) | |
| tree | 2f8494d4680579cd7a21bc899a0f6011c97d64bb /src/mainboard/tyan/s2850/irq_tables.c | |
| parent | 12eee5111f4a6ba87f48bb7db9c7d42f1ea77d07 (diff) | |
| download | coreboot-f0721563b48ff7e2ad1bd7398da2747ec1a3b055.tar.xz | |
Tyan mainboard changes form YhLu
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1326 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2850/irq_tables.c')
| -rw-r--r-- | src/mainboard/tyan/s2850/irq_tables.c | 36 |
1 files changed, 36 insertions, 0 deletions
diff --git a/src/mainboard/tyan/s2850/irq_tables.c b/src/mainboard/tyan/s2850/irq_tables.c new file mode 100644 index 0000000000..3f1e5bdf24 --- /dev/null +++ b/src/mainboard/tyan/s2850/irq_tables.c @@ -0,0 +1,36 @@ +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*12, /* there can be total 12 devices on the bus */ + 1, /* Where the interrupt router lies (bus) */ + (2<<3)|3, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x1022, /* Vendor */ + 0x746b, /* Device */ + 0, /* Crap (miniport) */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x9b, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + {1,(2<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0}, + {0x2,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0}, + {0x2,0x68, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x2,0x58, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x2,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0}, + {0x2,0x30, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x1, 0}, + {0x2,0x38, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x2, 0}, + {0x2,0x40, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0}, + {0x2,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x4, 0}, + {0x2,0x50, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x5, 0}, + {0x2,0x70, {{0x1, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + {0x2,0x60, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0}, + } +}; |