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author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-03-17 22:44:39 +0000 |
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committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-03-17 22:44:39 +0000 |
commit | ce6fb1ee2b37193fa828b4c6d475e23c58171346 (patch) | |
tree | 7207e49edde04fefd1a9208a73135d7a27c7b3dc /src/mainboard/tyan/s2850/romstage.c | |
parent | 78b40335841eae958865f67ac8ee0020fd43aead (diff) | |
download | coreboot-ce6fb1ee2b37193fa828b4c6d475e23c58171346.tar.xz |
Remove failover/fallback/normal handling in mainboards'
romstage.c. That's newconfig stuff.
1. In failover_process(), I removed the fallback/normal selection logic
and kept the remaining hardware init in. The if-clauses' conditions are
reverted to match.
Remove #if failover||fallback guard.
2. Change cache_as_ram_main() to first call failover_process, then
real_main unconditionally.
3. Move failover_process's code to the beginning of real_main, remove
failover_process and its call in cache_as_ram_main.
4. Remove cache_as_ram_main, rename real_main to cache_as_ram_main (same
arguments, so no problem with that)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5255 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2850/romstage.c')
0 files changed, 0 insertions, 0 deletions