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authorStefan Reinauer <stepan@coresystems.de>2010-04-27 06:56:47 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-27 06:56:47 +0000
commit14e22779625de673569c7b950ecc2753fb915b31 (patch)
tree14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/mainboard/tyan/s2850
parent0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff)
downloadcoreboot-14e22779625de673569c7b950ecc2753fb915b31.tar.xz
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2850')
-rw-r--r--src/mainboard/tyan/s2850/devicetree.cb20
-rw-r--r--src/mainboard/tyan/s2850/irq_tables.c2
-rw-r--r--src/mainboard/tyan/s2850/mptable.c14
-rw-r--r--src/mainboard/tyan/s2850/romstage.c6
4 files changed, 21 insertions, 21 deletions
diff --git a/src/mainboard/tyan/s2850/devicetree.cb b/src/mainboard/tyan/s2850/devicetree.cb
index 264f8c7df6..98e6a28746 100644
--- a/src/mainboard/tyan/s2850/devicetree.cb
+++ b/src/mainboard/tyan/s2850/devicetree.cb
@@ -1,9 +1,9 @@
chip northbridge/amd/amdk8/root_complex
- device apic_cluster 0 on
- chip cpu/amd/socket_940
- device apic 0 on end
- end
- end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
device pci_domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on # LDT0
@@ -51,7 +51,7 @@ chip northbridge/amd/amdk8/root_complex
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
- end
+ end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
@@ -63,7 +63,7 @@ chip northbridge/amd/amdk8/root_complex
end
device pci 1.1 on end
device pci 1.2 on end
- device pci 1.3 on
+ device pci 1.3 on
chip drivers/generic/generic #dimm 0-0-0
device i2c 50 on end
end
@@ -82,14 +82,14 @@ chip northbridge/amd/amdk8/root_complex
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end
- end # device pci 18.0
+ end # device pci 18.0
device pci 18.0 on end
device pci 18.0 on end
-
+
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end
- end
+ end
end
diff --git a/src/mainboard/tyan/s2850/irq_tables.c b/src/mainboard/tyan/s2850/irq_tables.c
index 8c7e681ec2..d1179dcfae 100644
--- a/src/mainboard/tyan/s2850/irq_tables.c
+++ b/src/mainboard/tyan/s2850/irq_tables.c
@@ -1,4 +1,4 @@
-/* This file was generated by getpir.c, do not modify!
+/* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify)
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
diff --git a/src/mainboard/tyan/s2850/mptable.c b/src/mainboard/tyan/s2850/mptable.c
index 0d4d6f9bc1..51c060126f 100644
--- a/src/mainboard/tyan/s2850/mptable.c
+++ b/src/mainboard/tyan/s2850/mptable.c
@@ -29,7 +29,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
dst_node = (config_map >> 4) & 7;
dst_link = (config_map >> 8) & 3;
bus_base = (config_map >> 16) & 0xff;
-#if 0
+#if 0
printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
dst_node, dst_link, bus_base,
reg, config_map);
@@ -90,8 +90,8 @@ static void *smp_write_config_table(void *v)
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
- }
- else {
+ }
+ else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
bus_8111_1 = 2;
@@ -110,12 +110,12 @@ static void *smp_write_config_table(void *v)
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+ apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
- apicid_8111 = apicid_base+0;
+ apicid_8111 = apicid_base+0;
smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
-
+
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0);
@@ -133,7 +133,7 @@ static void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (2<<2)|3, apicid_8111, 0x13);
-
+
//On Board AMD USB
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c
index 6fbafa90cb..4e75e36832 100644
--- a/src/mainboard/tyan/s2850/romstage.c
+++ b/src/mainboard/tyan/s2850/romstage.c
@@ -1,4 +1,4 @@
-
+
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -114,7 +114,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
}
// post_code(0x32);
-
+
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -125,7 +125,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
-
+
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();