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authorUwe Hermann <uwe@hermann-uwe.de>2010-11-26 22:35:11 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-26 22:35:11 +0000
commit1f7d3c5672ec90f8d71907b1a07c8a87fa461047 (patch)
treeb9e14e6c08cdcc52b4fa00cfe730fffa55ae137e /src/mainboard/tyan/s2850
parentdf323fcefd6020f8f418a13d65a075d282eed3de (diff)
downloadcoreboot-1f7d3c5672ec90f8d71907b1a07c8a87fa461047.tar.xz
AMD-8111: Add TINY_BOOTBLOCK support.
Also, add missing license header to amd8111_enable_rom.c, add some more code comments and use PCI IDs from pci_ids.h instead of hardcoding. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2850')
-rw-r--r--src/mainboard/tyan/s2850/romstage.c2
1 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/tyan/s2850/romstage.c b/src/mainboard/tyan/s2850/romstage.c
index 4f78797030..b7f0716796 100644
--- a/src/mainboard/tyan/s2850/romstage.c
+++ b/src/mainboard/tyan/s2850/romstage.c
@@ -59,7 +59,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -82,7 +81,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
- amd8111_enable_rom();
}
if (bist == 0)