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authorStefan Reinauer <stepan@coresystems.de>2010-04-27 06:56:47 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-27 06:56:47 +0000
commit14e22779625de673569c7b950ecc2753fb915b31 (patch)
tree14a6ed759e116e9e6e9bbd7f499b74b96d6cc072 /src/mainboard/tyan/s2875
parent0e1e8065e303030c39c3f2c27e5d32ee58a16c66 (diff)
downloadcoreboot-14e22779625de673569c7b950ecc2753fb915b31.tar.xz
Since some people disapprove of white space cleanups mixed in regular commits
while others dislike them being extra commits, let's clean them up once and for all for the existing code. If it's ugly, let it only be ugly once :-) Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2875')
-rw-r--r--src/mainboard/tyan/s2875/devicetree.cb12
-rw-r--r--src/mainboard/tyan/s2875/irq_tables.c2
-rw-r--r--src/mainboard/tyan/s2875/mptable.c16
-rw-r--r--src/mainboard/tyan/s2875/romstage.c4
4 files changed, 17 insertions, 17 deletions
diff --git a/src/mainboard/tyan/s2875/devicetree.cb b/src/mainboard/tyan/s2875/devicetree.cb
index badb881777..edd4f6f784 100644
--- a/src/mainboard/tyan/s2875/devicetree.cb
+++ b/src/mainboard/tyan/s2875/devicetree.cb
@@ -6,7 +6,7 @@ chip northbridge/amd/amdk8/root_complex
end
device pci_domain 0 on
chip northbridge/amd/amdk8
- device pci 18.0 on # northbridge
+ device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0
chip southbridge/amd/amd8151
# the on/off keyword is mandatory
@@ -55,7 +55,7 @@ chip northbridge/amd/amdk8/root_complex
io 0x60 = 0x220
io 0x62 = 0x300
irq 0x70 = 9
- end
+ end
device pnp 2e.8 off end # GPIO2
device pnp 2e.9 off end # GPIO3
device pnp 2e.a off end # ACPI
@@ -73,15 +73,15 @@ chip northbridge/amd/amdk8/root_complex
register "ide0_enable" = "1"
register "ide1_enable" = "1"
end
- end # device pci 18.0
-
+ end # device pci 18.0
+
device pci 18.0 on end
device pci 18.0 on end
-
+
device pci 18.1 on end
device pci 18.2 on end
device pci 18.3 on end
end
- end
+ end
end
diff --git a/src/mainboard/tyan/s2875/irq_tables.c b/src/mainboard/tyan/s2875/irq_tables.c
index db30d686c8..d08aa6ca09 100644
--- a/src/mainboard/tyan/s2875/irq_tables.c
+++ b/src/mainboard/tyan/s2875/irq_tables.c
@@ -1,4 +1,4 @@
-/* This file was generated by getpir.c, do not modify!
+/* This file was generated by getpir.c, do not modify!
(but if you do, please run checkpir on it to verify)
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
diff --git a/src/mainboard/tyan/s2875/mptable.c b/src/mainboard/tyan/s2875/mptable.c
index 77afde6abf..c2a7012f13 100644
--- a/src/mainboard/tyan/s2875/mptable.c
+++ b/src/mainboard/tyan/s2875/mptable.c
@@ -28,7 +28,7 @@ static unsigned node_link_to_bus(unsigned node, unsigned link)
dst_node = (config_map >> 4) & 7;
dst_link = (config_map >> 8) & 3;
bus_base = (config_map >> 16) & 0xff;
-#if 0
+#if 0
printk(BIOS_DEBUG, "node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
dst_node, dst_link, bus_base,
reg, config_map);
@@ -104,15 +104,15 @@ static void *smp_write_config_table(void *v)
if (dev) {
bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151_1);
-
+
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
bus_8151_1 = 2;
}
-
-
+
+
}
/*Bus: Bus ID Type*/
@@ -126,11 +126,11 @@ static void *smp_write_config_table(void *v)
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+ apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
#endif
- apicid_8111 = apicid_base+0;
+ apicid_8111 = apicid_base+0;
smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
-
+
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1);
@@ -156,7 +156,7 @@ static void *smp_write_config_table(void *v)
// AGP Display Adapter
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, apicid_8111, 0x10);
-// Onboard Serial ATA
+// Onboard Serial ATA
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x05<<2)|0, apicid_8111, 0x13);
//Onboard Firewire
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, apicid_8111, 0x11);
diff --git a/src/mainboard/tyan/s2875/romstage.c b/src/mainboard/tyan/s2875/romstage.c
index 274f8dc7ca..ead3655fae 100644
--- a/src/mainboard/tyan/s2875/romstage.c
+++ b/src/mainboard/tyan/s2875/romstage.c
@@ -1,4 +1,4 @@
-
+
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -135,7 +135,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
-
+
#if CONFIG_LOGICAL_CPUS==1
// It is said that we should start core1 after all core0 launched
start_other_cores();