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authorarch import user (historical) <svn@openbios.org>2005-07-06 16:49:52 +0000
committerarch import user (historical) <svn@openbios.org>2005-07-06 16:49:52 +0000
commit72c3b053d86c68a9e5454a79f0808c898170e21e (patch)
tree80fd2f9bfd9b0d22d1cc23685a65897c95ab62c3 /src/mainboard/tyan/s2880/Config.lb
parentfd6067425858d136418986fa77927a6ea76b79ee (diff)
downloadcoreboot-72c3b053d86c68a9e5454a79f0808c898170e21e.tar.xz
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-7
Creator: Yinghai Lu <yhlu@tyan.com> ide_enable in MB Config and jmp_auto ( it will make start in the 64k boundary) git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2880/Config.lb')
-rw-r--r--src/mainboard/tyan/s2880/Config.lb47
1 files changed, 27 insertions, 20 deletions
diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb
index 241e9d9968..f82bd23b44 100644
--- a/src/mainboard/tyan/s2880/Config.lb
+++ b/src/mainboard/tyan/s2880/Config.lb
@@ -121,20 +121,34 @@ mainboardinit cpu/x86/mmx/disable_mmx.inc
##
## Include the secondary Configuration files
##
-dir /pc80
if CONFIG_CHIP_NAME
config chip.h
end
# sample config for tyan/s2880
chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
device pci_domain 0 on
chip northbridge/amd/amdk8
device pci 18.0 on # northbridge
# devices on link 0, link 0 == LDT 0
chip southbridge/amd/amd8131
# the on/off keyword is mandatory
- device pci 0.0 on end
+ device pci 0.0 on
+ chip drivers/pci/onboard
+ device pci 9.0 on end #broadcom
+ device pci 9.1 on end
+ end
+ chip drivers/lsi/53c1030
+ device pci a.0 on end
+ device pci a.1 on end
+ register "fw_address" = "0xfff8c000"
+ end
+ end
device pci 0.1 on end
device pci 1.0 on end
device pci 1.1 on end
@@ -147,6 +161,13 @@ chip northbridge/amd/amdk8/root_complex
device pci 0.1 on end
device pci 0.2 off end
device pci 1.0 off end
+ chip drivers/pci/onboard
+ device pci 5.0 on end #some sata
+ end
+ chip drivers/pci/onboard
+ device pci 6.0 on end #adti
+ register "rom_address" = "0xfff80000"
+ end
end
device pci 1.0 on
chip superio/winbond/w83627hf
@@ -177,8 +198,8 @@ chip northbridge/amd/amdk8/root_complex
io 0x60 = 0x100
end
device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x201
- io 0x62 = 0x330
+ io 0x60 = 0x220
+ io 0x62 = 0x300
irq 0x70 = 9
end
device pnp 2e.8 off end # GPIO2
@@ -195,6 +216,8 @@ chip northbridge/amd/amdk8/root_complex
device pci 1.3 on end
device pci 1.5 off end
device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
end
end # device pci 18.0
@@ -205,22 +228,6 @@ chip northbridge/amd/amdk8/root_complex
device pci 18.2 on end
device pci 18.3 on end
end
- chip northbridge/amd/amdk8
- device pci 19.0 on end
- device pci 19.0 on end
- device pci 19.0 on end
- device pci 19.1 on end
- device pci 19.2 on end
- device pci 19.3 on end
- end
end
- device apic_cluster 0 on
- chip cpu/amd/socket_940
- device apic 0 on end
- end
- chip cpu/amd/socket_940
- device apic 1 on end
- end
- end
end