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authorRonald G. Minnich <rminnich@gmail.com>2004-03-12 15:13:38 +0000
committerRonald G. Minnich <rminnich@gmail.com>2004-03-12 15:13:38 +0000
commite4fc0ab250bd88ad8833a90d9338fd5b35881ebc (patch)
tree7ac09324ee465b31f5bfb1ed6a479c301e0de53d /src/mainboard/tyan/s2880/auto.c
parenta40a17c50cd10afea78bc5c1e41e486b9c4aa078 (diff)
downloadcoreboot-e4fc0ab250bd88ad8833a90d9338fd5b35881ebc.tar.xz
fixes for tyan
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2880/auto.c')
-rw-r--r--src/mainboard/tyan/s2880/auto.c95
1 files changed, 43 insertions, 52 deletions
diff --git a/src/mainboard/tyan/s2880/auto.c b/src/mainboard/tyan/s2880/auto.c
index 2d3f1fb3ae..c1d9d7e574 100644
--- a/src/mainboard/tyan/s2880/auto.c
+++ b/src/mainboard/tyan/s2880/auto.c
@@ -1,13 +1,17 @@
#define ASSEMBLY 1
+
#include <stdint.h>
#include <device/pci_def.h>
-#include <cpu/p6/apic.h>
#include <arch/io.h>
+#include <device/pnp_def.h>
#include <arch/romcc_io.h>
+#include <arch/smp/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "ram/ramtest.c"
-#include "northbridge/amd/amdk8/early_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/k8/apic_timer.c"
@@ -16,8 +20,25 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "debug.c"
#include "northbridge/amd/amdk8/cpu_rev.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+static void hard_reset(void)
+{
+ set_bios_reset();
+
+ /* enable cf9 */
+ pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+ /* reset */
+ outb(0x0e, 0x0cf9);
+}
+static void soft_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+}
#define REV_B_RESET 0
static void memreset_setup(void)
{
@@ -95,45 +116,10 @@ static inline int spd_read_byte(unsigned device, unsigned address)
/* include mainboard specific ht code */
#include "hypertransport.c"
-//#include "northbridge/amd/amdk8/cpu_ldtstop.c"
-//#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
-
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
-static void enable_lapic(void)
-{
- msr_t msr;
- msr = rdmsr(0x1b);
- msr.hi &= 0xffffff00;
- msr.lo &= 0x000007ff;
- msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
- wrmsr(0x1b, msr);
-}
-
-static void stop_this_cpu(void)
-{
- unsigned apicid;
- apicid = apic_read(APIC_ID) >> 24;
-
- /* Send an APIC INIT to myself */
- apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
- apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
- /* Wait for the ipi send to finish */
- apic_wait_icr_idle();
-
- /* Deassert the APIC INIT */
- apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
- apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
- /* Wait for the ipi send to finish */
- apic_wait_icr_idle();
-
- /* If I haven't halted spin forever */
- for(;;) {
- hlt();
- }
-}
#define FIRST_CPU 1
#define SECOND_CPU 1
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
@@ -163,21 +149,26 @@ static void main(void)
},
#endif
};
- if (cpu_init_detected()) {
- asm("jmp __cpu_reset");
- }
- enable_lapic();
- init_timer();
- if (!boot_cpu() ) {
-// notify_bsp_ap_is_stopped();
- stop_this_cpu();
- }
- uart_init();
- console_init();
- setup_default_resource_map();
- setup_coherent_ht_domain();
- enumerate_ht_chain(0);
- distinguish_cpu_resets(0);
+ int needs_reset;
+ enable_lapic();
+ init_timer();
+ if (cpu_init_detected()) {
+ asm("jmp __cpu_reset");
+ }
+ distinguish_cpu_resets();
+ if (!boot_cpu()) {
+ stop_this_cpu();
+ }
+ w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ uart_init();
+ console_init();
+ setup_default_resource_map();
+ needs_reset = setup_coherent_ht_domain();
+ needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+ if (needs_reset) {
+ print_info("ht reset -");
+ soft_reset();
+ }
#if 0
print_pci_devices();