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authorYinghai Lu <yinghailu@gmail.com>2005-07-08 02:49:49 +0000
committerYinghai Lu <yinghailu@gmail.com>2005-07-08 02:49:49 +0000
commit13f1c2af8be2cd7f7e99a678f5d428a65b771811 (patch)
tree27cad5581f1fa150f573149d48e82f70ba1b1d9f /src/mainboard/tyan/s2880
parent14cde9e96a777f9d75016a13b23fab0480515f58 (diff)
downloadcoreboot-13f1c2af8be2cd7f7e99a678f5d428a65b771811.tar.xz
eric patch
1. x86_setup_mtrr take address bit. 2. generic ht, pcix, pcie beidge... 3. scan bus and reset_bus 4. ht read ctrl to decide if the ht chain is ready 5. Intel e7520 and e7525 support 6. new ich5r support 7. intel sb 6300 support. yhlu patch 1. split x86_setup_mtrrs to fixed and var 2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource 3. in_conherent.c K8_SCAN_PCI_BUS git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2880')
-rw-r--r--src/mainboard/tyan/s2880/Config.lb71
-rw-r--r--src/mainboard/tyan/s2880/Options.lb28
-rw-r--r--src/mainboard/tyan/s2880/auto.c42
-rw-r--r--src/mainboard/tyan/s2880/irq_tables.c2
-rw-r--r--src/mainboard/tyan/s2880/mptable.c56
-rw-r--r--src/mainboard/tyan/s2880/reset.c6
6 files changed, 175 insertions, 30 deletions
diff --git a/src/mainboard/tyan/s2880/Config.lb b/src/mainboard/tyan/s2880/Config.lb
index 6c4ac7b7c1..f7ad508347 100644
--- a/src/mainboard/tyan/s2880/Config.lb
+++ b/src/mainboard/tyan/s2880/Config.lb
@@ -39,10 +39,33 @@ arch i386 end
##
driver mainboard.o
+
+#dir /drivers/si/3114
+
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-#object reset.o
+object reset.o
+
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o auto.o"
+end
+
+else
+
+makerule ./auto.inc
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+ action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+end
+end
+else
##
## Romcc output
@@ -66,13 +89,22 @@ makerule ./auto.inc
action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
+end
##
## Build our 16 bit and 32 bit linuxBIOS entry code
##
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
+if USE_DCACHE_RAM
+ if CONFIG_USE_INIT
+ ldscript /cpu/x86/32bit/entry32.lds
+ end
+
+ if CONFIG_USE_INIT
+ ldscript /cpu/amd/car/cache_as_ram.lds
+ end
+end
##
## Build our reset vector (This is where linuxBIOS is entered)
@@ -85,8 +117,11 @@ else
ldscript /cpu/x86/32bit/reset32.lds
end
+if USE_DCACHE_RAM
+else
### Should this be in the northbridge code?
mainboardinit arch/i386/lib/cpu_reset.inc
+end
##
## Include an id string (For safe flashing)
@@ -94,14 +129,25 @@ mainboardinit arch/i386/lib/cpu_reset.inc
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
+if USE_DCACHE_RAM
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
###
### This is the early phase of linuxBIOS startup
### Things are delicate and we test to see if we should
### failover to another image.
###
if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
+if USE_DCACHE_RAM
+ ldscript /arch/i386/lib/failover.lds
+else
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+end
end
###
@@ -111,6 +157,19 @@ end
##
## Setup RAM
##
+if USE_DCACHE_RAM
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+else
+
+##
+## Setup RAM
+##
mainboardinit cpu/x86/fpu/enable_fpu.inc
mainboardinit cpu/x86/mmx/enable_mmx.inc
mainboardinit cpu/x86/sse/enable_sse.inc
@@ -118,11 +177,13 @@ mainboardinit ./auto.inc
mainboardinit cpu/x86/sse/disable_sse.inc
mainboardinit cpu/x86/mmx/disable_mmx.inc
+end
+
##
## Include the secondary Configuration files
##
if CONFIG_CHIP_NAME
- config chip.h
+ config chip.h
end
# sample config for tyan/s2880
diff --git a/src/mainboard/tyan/s2880/Options.lb b/src/mainboard/tyan/s2880/Options.lb
index a6b4e86f50..1f929b0edc 100644
--- a/src/mainboard/tyan/s2880/Options.lb
+++ b/src/mainboard/tyan/s2880/Options.lb
@@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE
uses USE_FALLBACK_IMAGE
uses HAVE_FALLBACK_BOOT
uses HAVE_HARD_RESET
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
@@ -47,6 +44,7 @@ uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
uses HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
+uses CONFIG_GDB_STUB
uses CROSS_COMPILE
uses CC
uses HOSTCC
@@ -56,6 +54,9 @@ uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
uses K8_E0_MEM_HOLE_SIZEK
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
###
@@ -83,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1
default HAVE_HARD_RESET=1
##
-## Funky hard reset implementation
-##
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-
-##
## Build code to export a programmable irq routing table
##
default HAVE_PIRQ_TABLE=1
@@ -122,6 +116,9 @@ default CONFIG_MAX_CPUS=2
default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=0
+#CHIP_NAME ?
+default CONFIG_CHIP_NAME=1
+
#1G memory hole
default K8_E0_MEM_HOLE_SIZEK=0x100000
@@ -129,6 +126,15 @@ default K8_E0_MEM_HOLE_SIZEK=0x100000
default CONFIG_CONSOLE_VGA=1
default CONFIG_PCI_ROM_RUN=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xcf000
+default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_INIT=1
+
##
## Build code to setup a generic IOAPIC
##
@@ -137,7 +143,7 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="s2880"
+default MAINBOARD_PART_NUMBER="S2880"
default MAINBOARD_VENDOR="Tyan"
default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2880
diff --git a/src/mainboard/tyan/s2880/auto.c b/src/mainboard/tyan/s2880/auto.c
index 1ed43bc19e..2532386132 100644
--- a/src/mainboard/tyan/s2880/auto.c
+++ b/src/mainboard/tyan/s2880/auto.c
@@ -27,20 +27,52 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+/* Look up a which bus a given node/link combination is on.
+ * return 0 when we can't find the answer.
+ */
+static unsigned node_link_to_bus(unsigned node, unsigned link)
+{
+ unsigned reg;
+
+ for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+ unsigned config_map;
+ config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
+ if ((config_map & 3) != 3) {
+ continue;
+ }
+ if ((((config_map >> 4) & 7) == node) &&
+ (((config_map >> 8) & 3) == link))
+ {
+ return (config_map >> 16) & 0xff;
+ }
+ }
+ return 0;
+}
+
static void hard_reset(void)
{
+ device_t dev;
+
+ /* Find the device */
+ dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
+
set_bios_reset();
/* enable cf9 */
- pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+ pci_write_config8(dev, 0x41, 0xf1);
/* reset */
outb(0x0e, 0x0cf9);
}
static void soft_reset(void)
{
+ device_t dev;
+
+ /* Find the device */
+ dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
+
set_bios_reset();
- pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+ pci_write_config8(dev, 0x47, 1);
}
static void memreset_setup(void)
@@ -155,7 +187,7 @@ static void main(unsigned long bist)
|| (id.coreid != 0)
#endif
) {
- stop_this_cpu();
+ stop_this_cpu(); // it will stop all cores except core0 of cpu0
}
}
@@ -179,8 +211,4 @@ static void main(unsigned long bist)
soft_reset();
}
- enable_smbus();
- memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
-
}
diff --git a/src/mainboard/tyan/s2880/irq_tables.c b/src/mainboard/tyan/s2880/irq_tables.c
index 4ffc5cffa0..08c51795fd 100644
--- a/src/mainboard/tyan/s2880/irq_tables.c
+++ b/src/mainboard/tyan/s2880/irq_tables.c
@@ -37,5 +37,5 @@ const struct irq_routing_table intel_irq_routing_table = {
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
- return copy_pirq_routing_table(addr);
+ return copy_pirq_routing_table(addr);
}
diff --git a/src/mainboard/tyan/s2880/mptable.c b/src/mainboard/tyan/s2880/mptable.c
index 9c4764a77b..d013a463fa 100644
--- a/src/mainboard/tyan/s2880/mptable.c
+++ b/src/mainboard/tyan/s2880/mptable.c
@@ -7,6 +7,42 @@
#include <cpu/amd/dualcore.h>
#endif
+
+static unsigned node_link_to_bus(unsigned node, unsigned link)
+{
+ device_t dev;
+ unsigned reg;
+
+ dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
+ if (!dev) {
+ return 0;
+ }
+ for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+ uint32_t config_map;
+ unsigned dst_node;
+ unsigned dst_link;
+ unsigned bus_base;
+ config_map = pci_read_config32(dev, reg);
+ if ((config_map & 3) != 3) {
+ continue;
+ }
+ dst_node = (config_map >> 4) & 7;
+ dst_link = (config_map >> 8) & 3;
+ bus_base = (config_map >> 16) & 0xff;
+#if 0
+ printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
+ dst_node, dst_link, bus_base,
+ reg, config_map);
+#endif
+ if ((dst_node == node) && (dst_link == link))
+ {
+ return bus_base;
+ }
+ }
+ return 0;
+}
+
+
void *smp_write_config_table(void *v)
{
static const char sig[4] = "PCMP";
@@ -16,6 +52,7 @@ void *smp_write_config_table(void *v)
unsigned char bus_num;
unsigned char bus_isa;
+ unsigned char bus_chain_0;
unsigned char bus_8131_1;
unsigned char bus_8131_2;
unsigned char bus_8111_1;
@@ -45,9 +82,16 @@ void *smp_write_config_table(void *v)
{
device_t dev;
+
+ /* HT chain 0 */
+ bus_chain_0 = node_link_to_bus(0, 0);
+ if (bus_chain_0 == 0) {
+ printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
+ bus_chain_0 = 1;
+ }
/* 8111 */
- dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
+ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
@@ -60,7 +104,7 @@ void *smp_write_config_table(void *v)
bus_isa = 5;
}
/* 8131-1 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
+ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
@@ -71,7 +115,7 @@ void *smp_write_config_table(void *v)
bus_8131_1 = 2;
}
/* 8131-2 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
+ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
@@ -105,14 +149,14 @@ void *smp_write_config_table(void *v)
device_t dev;
struct resource *res;
- dev = dev_find_slot(1, PCI_DEVFN(0x1,1));
+ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
}
}
- dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
+ dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
@@ -137,7 +181,7 @@ void *smp_write_config_table(void *v)
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 1, (4<<2)|0, apicid_8111, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|0, apicid_8111, 0x13);
//On Board AMD USB
diff --git a/src/mainboard/tyan/s2880/reset.c b/src/mainboard/tyan/s2880/reset.c
new file mode 100644
index 0000000000..3db3956ec6
--- /dev/null
+++ b/src/mainboard/tyan/s2880/reset.c
@@ -0,0 +1,6 @@
+#include "../../../southbridge/amd/amd8111/amd8111_reset.c"
+
+void hard_reset(void)
+{
+ amd8111_hard_reset(0, 0);
+}