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authorStefan Reinauer <stepan@coresystems.de>2009-06-30 15:17:49 +0000
committerStefan Reinauer <stepan@openbios.org>2009-06-30 15:17:49 +0000
commit0867062412dd4bfe5a556e5f3fd85ba5b682d79b (patch)
tree81ca5db12b8567b48daaa23a541bfb8a5dc011f8 /src/mainboard/tyan/s2881
parent9702b6bf7ec5a4fb16934f1cf2724480e2460c89 (diff)
downloadcoreboot-0867062412dd4bfe5a556e5f3fd85ba5b682d79b.tar.xz
This patch unifies the use of config options in v2 to all start with CONFIG_
It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2881')
-rw-r--r--src/mainboard/tyan/s2881/Config.lb22
-rw-r--r--src/mainboard/tyan/s2881/Options.lb190
-rw-r--r--src/mainboard/tyan/s2881/cache_as_ram_auto.c6
-rw-r--r--src/mainboard/tyan/s2881/get_bus_conf.c4
4 files changed, 111 insertions, 111 deletions
diff --git a/src/mainboard/tyan/s2881/Config.lb b/src/mainboard/tyan/s2881/Config.lb
index f9ac2a2570..6480067300 100644
--- a/src/mainboard/tyan/s2881/Config.lb
+++ b/src/mainboard/tyan/s2881/Config.lb
@@ -1,5 +1,5 @@
-## XIP_ROM_SIZE must be a power of 2.
-default XIP_ROM_SIZE = 64 * 1024
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
include /config/nofailovercalculation.lb
arch i386 end
@@ -12,21 +12,21 @@ driver mainboard.o
#dir /drivers/si/3114
object get_bus_conf.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
if CONFIG_USE_INIT
makerule ./auto.o
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
end
else
makerule ./auto.inc
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(MAINBOARD)/cache_as_ram_auto.c -o $@"
+ depends "$(CONFIG_MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/cache_as_ram_auto.c -o $@"
action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
end
@@ -35,7 +35,7 @@ end
##
## Build our 16 bit and 32 bit coreboot entry code
##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/entry16.inc
ldscript /cpu/x86/16bit/entry16.lds
end
@@ -53,7 +53,7 @@ mainboardinit cpu/x86/32bit/entry32.inc
##
## Build our reset vector (This is where coreboot is entered)
##
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
mainboardinit cpu/x86/16bit/reset16.inc
ldscript /cpu/x86/16bit/reset16.lds
else
@@ -77,7 +77,7 @@ mainboardinit cpu/amd/car/cache_as_ram.inc
### Things are delicate and we test to see if we should
### failover to another image.
###
-if USE_FALLBACK_IMAGE
+if CONFIG_USE_FALLBACK_IMAGE
ldscript /arch/i386/lib/failover.lds
end
diff --git a/src/mainboard/tyan/s2881/Options.lb b/src/mainboard/tyan/s2881/Options.lb
index d83638715b..18087be3d3 100644
--- a/src/mainboard/tyan/s2881/Options.lb
+++ b/src/mainboard/tyan/s2881/Options.lb
@@ -1,69 +1,69 @@
-uses HAVE_MP_TABLE
+uses CONFIG_HAVE_MP_TABLE
uses CONFIG_CBFS
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
uses CONFIG_MAX_PHYSICAL_CPUS
uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
uses CONFIG_ROM_PAYLOAD
uses CONFIG_ROM_PAYLOAD_START
uses CONFIG_COMPRESSED_PAYLOAD_LZMA
uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses CONFIG_PAYLOAD_SIZE
+uses CONFIG_ROMBASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
uses COREBOOT_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_RAMBASE
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
+uses CONFIG_HAVE_INIT_TIMER
uses CONFIG_GDB_STUB
uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
+uses CONFIG_CROSS_COMPILE
uses CC
-uses HOSTCC
-uses OBJCOPY
+uses CONFIG_HOSTCC
+uses CONFIG_OBJCOPY
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
+uses CONFIG_HW_MEM_HOLE_SIZEK
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+uses CONFIG_HT_CHAIN_UNITID_BASE
+uses CONFIG_HT_CHAIN_END_UNITID_BASE
+uses CONFIG_SB_HT_CHAIN_ON_BUS0
+uses CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
uses CONFIG_USE_PRINTK_IN_CAR
@@ -72,50 +72,50 @@ uses CONFIG_USE_PRINTK_IN_CAR
###
##
-## ROM_SIZE is the size of boot ROM that this board will use.
+## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
##
-default ROM_SIZE=524288
+default CONFIG_ROM_SIZE=524288
##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+## CONFIG_FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
-#default FALLBACK_SIZE=131072
+#default CONFIG_FALLBACK_SIZE=131072
#256K
-default FALLBACK_SIZE=0x40000
+default CONFIG_FALLBACK_SIZE=0x40000
##
## Build code for the fallback boot
##
-default HAVE_FALLBACK_BOOT=1
+default CONFIG_HAVE_FALLBACK_BOOT=1
##
## Build code to reset the motherboard from coreboot
##
-default HAVE_HARD_RESET=1
+default CONFIG_HAVE_HARD_RESET=1
##
## Build code to export a programmable irq routing table
##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=9
##
## Build code to export an x86 MP table
## Useful for specifying IRQ routing values
##
-default HAVE_MP_TABLE=1
+default CONFIG_HAVE_MP_TABLE=1
##
## Build code to export a CMOS option table
##
-default HAVE_OPTION_TABLE=1
+default CONFIG_HAVE_OPTION_TABLE=1
##
## Move the default coreboot cmos range off of AMD RTC registers
##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
##
## Build code for SMP support
@@ -127,19 +127,19 @@ default CONFIG_MAX_PHYSICAL_CPUS=2
default CONFIG_LOGICAL_CPUS=1
##HT Unit ID offset, default is 1, the typical one
-default HT_CHAIN_UNITID_BASE=0x0a
+default CONFIG_HT_CHAIN_UNITID_BASE=0x0a
##real SB Unit ID, default is 0x20, mean dont touch it at last
-default HT_CHAIN_END_UNITID_BASE=0x06
+default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06
#make the SB HT chain on bus 0, default is not (0)
-default SB_HT_CHAIN_ON_BUS0=0
+default CONFIG_SB_HT_CHAIN_ON_BUS0=0
##only offset for SB chain?, default is yes(1)
-#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+#default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
#1G memory hole
-default HW_MEM_HOLE_SIZEK=0x100000
+default CONFIG_HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
@@ -149,9 +149,9 @@ default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xcf000
-default DCACHE_RAM_SIZE=0x1000
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_BASE=0xcf000
+default CONFIG_DCACHE_RAM_SIZE=0x1000
default CONFIG_USE_INIT=0
##
@@ -162,37 +162,37 @@ default CONFIG_IOAPIC=1
##
## Clean up the motherboard id strings
##
-default MAINBOARD_PART_NUMBER="s2881"
-default MAINBOARD_VENDOR="Tyan"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881
+default CONFIG_MAINBOARD_PART_NUMBER="s2881"
+default CONFIG_MAINBOARD_VENDOR="Tyan"
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
+default CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2881
###
### coreboot layout values
###
-## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default ROM_IMAGE_SIZE = 65536
+## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
##
## Use a small 8K stack
##
-default STACK_SIZE=0x2000
+default CONFIG_STACK_SIZE=0x2000
##
## Use a small 16K heap
##
-default HEAP_SIZE=0x4000
+default CONFIG_HEAP_SIZE=0x4000
##
## Only use the option table in a normal image
##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
##
## Coreboot C code runs at this location in RAM
##
-default _RAMBASE=0x00004000
+default CONFIG_RAMBASE=0x00004000
##
## Load the payload from the ROM
@@ -206,8 +206,8 @@ default CONFIG_ROM_PAYLOAD = 1
##
## The default compiler
##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
+default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
+default CONFIG_HOSTCC="gcc"
##
## Disable the gdb stub by default
@@ -224,21 +224,21 @@ default CONFIG_USE_PRINTK_IN_CAR=1
default CONFIG_CONSOLE_SERIAL8250=1
## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
# Select the serial console base port
-default TTYS0_BASE=0x3f8
+default CONFIG_TTYS0_BASE=0x3f8
# Select the serial protocol
# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
+default CONFIG_TTYS0_LCS=0x3
##
### Select the coreboot loglevel
@@ -250,17 +250,17 @@ default TTYS0_LCS=0x3
## WARNING 5 warning conditions
## NOTICE 6 normal but significant condition
## INFO 7 informational
-## DEBUG 8 debug-level messages
+## CONFIG_DEBUG 8 debug-level messages
## SPEW 9 Way too many details
## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=8
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=8
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8
##
## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
### End Options.lb
#
diff --git a/src/mainboard/tyan/s2881/cache_as_ram_auto.c b/src/mainboard/tyan/s2881/cache_as_ram_auto.c
index 0f853b8af1..9beb7afaeb 100644
--- a/src/mainboard/tyan/s2881/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2881/cache_as_ram_auto.c
@@ -99,7 +99,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
#include "cpu/amd/model_fxx/init_cpus.c"
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -155,7 +155,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
failover_process(bist, cpu_init_detectedx);
#endif
real_main(bist, cpu_init_detectedx);
@@ -185,7 +185,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
// post_code(0x32);
- w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
diff --git a/src/mainboard/tyan/s2881/get_bus_conf.c b/src/mainboard/tyan/s2881/get_bus_conf.c
index d4c01675ab..1ed1e0dbaa 100644
--- a/src/mainboard/tyan/s2881/get_bus_conf.c
+++ b/src/mainboard/tyan/s2881/get_bus_conf.c
@@ -82,7 +82,7 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
// printk_debug("bus_isa=%d\n",bus_isa);
@@ -105,7 +105,7 @@ void get_bus_conf(void)
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_isa++;
// printk_debug("bus_isa=%d\n",bus_isa);