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author | Ronald G. Minnich <rminnich@gmail.com> | 2004-03-12 15:13:38 +0000 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2004-03-12 15:13:38 +0000 |
commit | e4fc0ab250bd88ad8833a90d9338fd5b35881ebc (patch) | |
tree | 7ac09324ee465b31f5bfb1ed6a479c301e0de53d /src/mainboard/tyan/s2882/failover.c | |
parent | a40a17c50cd10afea78bc5c1e41e486b9c4aa078 (diff) | |
download | coreboot-e4fc0ab250bd88ad8833a90d9338fd5b35881ebc.tar.xz |
fixes for tyan
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2882/failover.c')
-rw-r--r-- | src/mainboard/tyan/s2882/failover.c | 74 |
1 files changed, 54 insertions, 20 deletions
diff --git a/src/mainboard/tyan/s2882/failover.c b/src/mainboard/tyan/s2882/failover.c index 8b8bcb8b12..b22abfea06 100644 --- a/src/mainboard/tyan/s2882/failover.c +++ b/src/mainboard/tyan/s2882/failover.c @@ -3,44 +3,78 @@ #include <device/pci_def.h> #include <device/pci_ids.h> #include <arch/io.h> -#include "arch/romcc_io.h" +#include <arch/romcc_io.h> +#include <arch/smp/lapic.h> #include "pc80/mc146818rtc_early.c" -#if 0 -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#endif #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" #include "cpu/p6/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" +#define HAVE_REGPARM_SUPPORT 0 +#if HAVE_REGPARM_SUPPORT +static unsigned long main(unsigned long bist) +{ +#else static void main(void) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ -#if 0 - uart_init(); - console_init(); + unsigned long bist = 0; #endif - enumerate_ht_chain(0); - - /* Setup the 8111 */ - amd8111_enable_rom(); + /* Make cerain my local apic is useable */ + enable_lapic(); - /* Is this a cpu reset? */ + /* Is this a cpu only reset? */ if (cpu_init_detected()) { if (last_boot_normal()) { - asm("jmp __normal_image"); + goto normal_image; } else { - asm("jmp __cpu_reset"); + goto cpu_reset; } } /* Is this a secondary cpu? */ - else if (!boot_cpu() && last_boot_normal()) { - asm("jmp __normal_image"); + if (!boot_cpu()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto fallback_image; + } + } + + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* Setup the 8111 */ + amd8111_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; } /* This is the primary cpu how should I boot? */ else if (do_normal_boot()) { - asm("jmp __normal_image"); + goto normal_image; } + else { + goto fallback_image; + } + normal_image: + asm("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: + asm("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); + fallback_image: +#if HAVE_REGPARM_SUPPORT + return bist; +#else + return; +#endif } |