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author | arch import user (historical) <svn@openbios.org> | 2005-07-06 18:17:35 +0000 |
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committer | arch import user (historical) <svn@openbios.org> | 2005-07-06 18:17:35 +0000 |
commit | 59140ccdf384346ab0a6112baee175a01ed5bd9f (patch) | |
tree | c4e0e610eef9aedcce0c5fea8170f107390d9fcd /src/mainboard/tyan/s2882/mptable.c | |
parent | 80e3d96d0aeb52a1e648d6ca3b88611469dd8584 (diff) | |
download | coreboot-59140ccdf384346ab0a6112baee175a01ed5bd9f.tar.xz |
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-61
Creator: Yinghai Lu <yhlu@tyan.com>
write_pirq_routing_table for x86
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2882/mptable.c')
-rw-r--r-- | src/mainboard/tyan/s2882/mptable.c | 142 |
1 files changed, 48 insertions, 94 deletions
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c index a331247fa9..6461a0be45 100644 --- a/src/mainboard/tyan/s2882/mptable.c +++ b/src/mainboard/tyan/s2882/mptable.c @@ -8,7 +8,40 @@ #include <cpu/amd/dualcore.h> #endif -#define ASSIGN_IRQ 0 + +static unsigned node_link_to_bus(unsigned node, unsigned link) +{ + device_t dev; + unsigned reg; + + dev = dev_find_slot(0, PCI_DEVFN(0x18, 1)); + if (!dev) { + return 0; + } + for(reg = 0xE0; reg < 0xF0; reg += 0x04) { + uint32_t config_map; + unsigned dst_node; + unsigned dst_link; + unsigned bus_base; + config_map = pci_read_config32(dev, reg); + if ((config_map & 3) != 3) { + continue; + } + dst_node = (config_map >> 4) & 7; + dst_link = (config_map >> 8) & 3; + bus_base = (config_map >> 16) & 0xff; +#if 0 + printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n", + dst_node, dst_link, bus_base, + reg, config_map); +#endif + if ((dst_node == node) && (dst_link == link)) + { + return bus_base; + } + } + return 0; +} void *smp_write_config_table(void *v) { @@ -19,6 +52,7 @@ void *smp_write_config_table(void *v) unsigned char bus_num; unsigned char bus_isa; + unsigned char bus_chain_0; unsigned char bus_8131_1; unsigned char bus_8131_2; unsigned char bus_8111_1; @@ -48,8 +82,15 @@ void *smp_write_config_table(void *v) { device_t dev; + /* HT chain 0 */ + bus_chain_0 = node_link_to_bus(0, 0); + if (bus_chain_0 == 0) { + printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n"); + bus_chain_0 = 1; + } + /* 8111 */ - dev = dev_find_slot(1, PCI_DEVFN(0x03,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0)); if (dev) { bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); @@ -62,7 +103,7 @@ void *smp_write_config_table(void *v) bus_isa = 5; } /* 8131-1 */ - dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -73,7 +114,7 @@ void *smp_write_config_table(void *v) bus_8131_1 = 2; } /* 8131-2 */ - dev = dev_find_slot(1, PCI_DEVFN(0x02,0)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0)); if (dev) { bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); @@ -106,14 +147,14 @@ void *smp_write_config_table(void *v) { device_t dev; struct resource *res; - dev = dev_find_slot(1, PCI_DEVFN(0x1,1)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x1,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base); } } - dev = dev_find_slot(1, PCI_DEVFN(0x2,1)); + dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x2,1)); if (dev) { res = find_resource(dev, PCI_BASE_ADDRESS_0); if (res) { @@ -137,50 +178,16 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf); -#if ASSIGN_IRQ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (4<<2)|3, apicid_8111, 0x13); - - { - device_t dev; - dev = dev_find_device(PCI_VENDOR_ID_AMD, 0x746b, 0); - if (dev) { - /* initialize PCI interupts - these assignments depend - on the PCB routing of PINTA-D - - PINTA = IRQ5 - PINTB = IRQ9 - PINTC = IRQ11 - PINTD = IRQ10 - */ - pci_write_config16(dev, 0x56, 0xab95); - } - } -#endif + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chain_0, (4<<2)|3, apicid_8111, 0x13); -#if ASSIGN_IRQ - printk_info("setting Onboard AMD Southbridge \n"); - static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 }; - pci_assign_irqs(1, 4, slotIrqs_1_4); -#endif //On Board AMD USB smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13); -#if ASSIGN_IRQ - printk_info("setting Onboard AMD USB \n"); - static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 }; - pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0); -#endif //On Board ATI Display Adapter smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12); -#if ASSIGN_IRQ - printk_info("setting Onboard ATI Display Adapter\n"); - static const unsigned char slotIrqs_8111_1_6[4] = { 11, 0, 0, 0 }; - pci_assign_irqs(bus_8111_1, 6, slotIrqs_8111_1_6); -#endif - #if 1 //Slot 5 PCI 32 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10); @@ -188,31 +195,13 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); // -#if ASSIGN_IRQ - printk_info("setting Slot 5 \n"); - static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 }; - pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4); -#endif - #endif //Onboard SI Serial ATA smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13); -#if ASSIGN_IRQ - printk_info("setting Onboard SI Serail ATA\n"); - static const unsigned char slotIrqs_8111_1_5[4] = { 10, 0, 0, 0 }; - pci_assign_irqs(bus_8111_1, 5, slotIrqs_8111_1_5); -#endif - //Onboard Intel 82551 10/100M NIC smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, apicid_8111, 0x12); -#if ASSIGN_IRQ - printk_info("setting Onboard Intel NIC\n"); - static const unsigned char slotIrqs_8111_1_8[4] = { 11, 0, 0, 0 }; - pci_assign_irqs(bus_8111_1, 8, slotIrqs_8111_1_8); -#endif - #if 1 //Slot 3 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3); @@ -220,46 +209,23 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);// -#if ASSIGN_IRQ - printk_info("setting Slot 3\n"); - static const unsigned char slotIrqs_8131_1_3[4] = { 10, 5, 9, 11 }; - pci_assign_irqs(bus_8131_1, 3, slotIrqs_8131_1_3); -#endif - //Slot 4 PCIX 100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);// -#if ASSIGN_IRQ - printk_info("setting Slot 4\n"); - static const unsigned char slotIrqs_8131_1_2[4] = { 11, 10, 5, 9 }; - pci_assign_irqs(bus_8131_1, 2, slotIrqs_8131_1_2); -#endif #endif //Onboard adaptec scsi smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|0, apicid_8131_1, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, apicid_8131_1, 0x1); -#if ASSIGN_IRQ - printk_info("setting Onboard Adaptec SCSI\n"); - static const unsigned char slotIrqs_8131_1_6[4] = { 5, 9, 0, 0 }; - pci_assign_irqs(bus_8131_1, 6, slotIrqs_8131_1_6); -#endif - //On Board NIC smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1); -#if ASSIGN_IRQ - printk_info("setting Onboard Broadcom NIC\n"); - static const unsigned char slotIrqs_8131_1_9[4] = { 5, 9, 0, 0 }; - pci_assign_irqs(bus_8131_1, 9, slotIrqs_8131_1_9); -#endif - #if 1 //Slot 1 PCI-X 133/100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0); @@ -267,24 +233,12 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); // smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); // -#if ASSIGN_IRQ - printk_info("setting Slot 1\n"); - static const unsigned char slotIrqs_8131_2_3[4] = { 5, 9, 11, 10 }; - pci_assign_irqs(bus_8131_2, 3, slotIrqs_8131_2_3); -#endif - //Slot 2 PCI-X 133/100/66 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);// smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);// -#if ASSIGN_IRQ - printk_info("setting Slot 2\n"); - static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 }; - pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1); -#endif - #endif /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); 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