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authorarch import user (historical) <svn@openbios.org>2005-07-06 17:15:30 +0000
committerarch import user (historical) <svn@openbios.org>2005-07-06 17:15:30 +0000
commitef03afa405b049a172146aab93cfb81fb21f3945 (patch)
tree3b59033be66edd60c2cc6c66d6875153dc052a72 /src/mainboard/tyan/s2882
parent014c3e185fe8e1455e56efeb496715a67ce292bb (diff)
downloadcoreboot-ef03afa405b049a172146aab93cfb81fb21f3945.tar.xz
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-34
Creator: Yinghai Lu <yhlu@tyan.com> AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2882')
-rw-r--r--src/mainboard/tyan/s2882/Options.lb18
-rw-r--r--src/mainboard/tyan/s2882/auto.c136
-rw-r--r--src/mainboard/tyan/s2882/cmos.layout1
-rw-r--r--src/mainboard/tyan/s2882/failover.c27
-rw-r--r--src/mainboard/tyan/s2882/mptable.c108
5 files changed, 140 insertions, 150 deletions
diff --git a/src/mainboard/tyan/s2882/Options.lb b/src/mainboard/tyan/s2882/Options.lb
index 5d7ac25eda..4f084c86ba 100644
--- a/src/mainboard/tyan/s2882/Options.lb
+++ b/src/mainboard/tyan/s2882/Options.lb
@@ -9,6 +9,8 @@ uses HARD_RESET_FUNCTION
uses IRQ_SLOT_COUNT
uses HAVE_OPTION_TABLE
uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
uses CONFIG_IOAPIC
uses CONFIG_SMP
uses FALLBACK_SIZE
@@ -50,6 +52,9 @@ uses CC
uses HOSTCC
uses OBJCOPY
uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses K8_E0_MEM_HOLE_SIZEK
###
### Build options
@@ -111,7 +116,16 @@ default LB_CKS_LOC=123
## Only worry about 2 micro processors
##
default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
+default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_LOGICAL_CPUS=1
+
+#1G memory hole
+default K8_E0_MEM_HOLE_SIZEK=0x100000
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1
##
## Build code to setup a generic IOAPIC
@@ -211,7 +225,7 @@ default TTYS0_LCS=0x3
## SPEW 9 Way too many details
## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=7
+default DEFAULT_CONSOLE_LOGLEVEL=8
## At a maximum only compile in this level of debugging
default MAXIMUM_CONSOLE_LOGLEVEL=8
diff --git a/src/mainboard/tyan/s2882/auto.c b/src/mainboard/tyan/s2882/auto.c
index db50fde657..fb7a63abb5 100644
--- a/src/mainboard/tyan/s2882/auto.c
+++ b/src/mainboard/tyan/s2882/auto.c
@@ -43,13 +43,6 @@ static void soft_reset(void)
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
}
-static void soft2_reset(void)
-{
- set_bios_reset();
- pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
-}
-
-
#define REV_B_RESET 0
static void memreset_setup(void)
{
@@ -72,50 +65,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
}
-static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
-{
- /* Routing Table Node i
- *
- * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
- * i: 0, 1, 2, 3, 4, 5, 6, 7
- *
- * [ 0: 3] Request Route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- * [11: 8] Response Route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- * [19:16] Broadcast route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- */
-
- uint32_t ret=0x00010101; /* default row entry */
- /* Link1 of CPU0 to Link1 of CPU1 */
- static const unsigned int rows_2p[2][2] = {
- { 0x00050101, 0x00010404 },
- { 0x00010404, 0x00050101 }
- };
-#if 0
- if(maxnodes>2) {
- printo_debug("this mainboard is only designed for 2 cpus\r\n");
- maxnodes=2;
- }
-#endif
-
- if (!(node>=maxnodes || row>=maxnodes)) {
- ret=rows_2p[node][row];
- }
-
- return ret;
-}
-
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
@@ -126,11 +75,17 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+#define K8_4RANK_DIMM_SUPPORT 1
#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "sdram/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#include "cpu/amd/dualcore/dualcore.c"
+#endif
#define FIRST_CPU 1
#define SECOND_CPU 1
@@ -167,22 +122,45 @@ static void main(unsigned long bist)
};
int needs_reset;
- unsigned nodeid;
+#if CONFIG_LOGICAL_CPUS==1
+ struct node_core_id id;
+#else
+ unsigned nodeid;
+#endif
if (bist == 0) {
/* Skip this if there was a built in self test failure */
amd_early_mtrr_init();
+
+#if CONFIG_LOGICAL_CPUS==1
+ set_apicid_cpuid_lo();
+#endif
+
enable_lapic();
init_timer();
- nodeid = lapicid() & 0xf;
-
+#if CONFIG_LOGICAL_CPUS==1
+ id = get_node_core_id_x();
+ if(id.coreid == 0) {
+ if (cpu_init_detected(id.nodeid)) {
+ asm volatile ("jmp __cpu_reset");
+ }
+ distinguish_cpu_resets(id.nodeid);
+ }
+#else
+ nodeid = lapicid();
if (cpu_init_detected(nodeid)) {
asm volatile ("jmp __cpu_reset");
}
distinguish_cpu_resets(nodeid);
- if (!boot_cpu()) {
- stop_this_cpu();
+#endif
+
+ if (!boot_cpu()
+#if CONFIG_LOGICAL_CPUS==1
+ || (id.coreid != 0)
+#endif
+ ) {
+ stop_this_cpu();
}
}
@@ -191,54 +169,22 @@ static void main(unsigned long bist)
console_init();
/* Halt if there was a built in self test failure */
- report_bist_failure(bist);
+// report_bist_failure(bist);
setup_default_resource_map();
needs_reset = setup_coherent_ht_domain();
- needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+#if CONFIG_LOGICAL_CPUS==1
+ start_other_cores();
+#endif
+ // automatically set that for you, but you might meet tight space
+ needs_reset |= ht_setup_chains_x();
if (needs_reset) {
print_info("ht reset -\r\n");
soft_reset();
}
-#if 0
- print_pci_devices();
-#endif
enable_smbus();
-#if 0
-// dump_spd_registers(&cpu[0]);
- dump_smbus_registers();
-#endif
memreset_setup();
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
-#if 0
- dump_pci_devices();
-#endif
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 1));
-#endif
-
- /* Check all of memory */
-#if 0
- msr_t msr;
- msr = rdmsr(TOP_MEM2);
- print_debug("TOP_MEM2: ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\r\n");
-#endif
-/*
-#if 0
- ram_check(0x00000000, msr.lo+(msr.hi<<32));
-#else
-#if TOTAL_CPUS < 2
- // Check 16MB of memory @ 0
- ram_check(0x00000000, 0x01000000);
-#else
- // Check 16MB of memory @ 2GB
- ram_check(0x80000000, 0x81000000);
-#endif
-#endif
-*/
}
diff --git a/src/mainboard/tyan/s2882/cmos.layout b/src/mainboard/tyan/s2882/cmos.layout
index ea027282c4..c1f3d75316 100644
--- a/src/mainboard/tyan/s2882/cmos.layout
+++ b/src/mainboard/tyan/s2882/cmos.layout
@@ -32,6 +32,7 @@ entries
395 1 e 1 hw_scrubber
396 1 e 1 interleave_chip_selects
397 2 e 8 max_mem_clock
+399 1 e 2 dual_core
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
416 4 e 7 boot_first
diff --git a/src/mainboard/tyan/s2882/failover.c b/src/mainboard/tyan/s2882/failover.c
index 45315521ac..9164e7b091 100644
--- a/src/mainboard/tyan/s2882/failover.c
+++ b/src/mainboard/tyan/s2882/failover.c
@@ -11,16 +11,30 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
+#if CONFIG_LOGICAL_CPUS==1
+#include "cpu/amd/dualcore/dualcore_id.c"
+#endif
+
+
static unsigned long main(unsigned long bist)
-{
+{
+#if CONFIG_LOGICAL_CPUS==1
+ struct node_core_id id;
+#else
unsigned nodeid;
+#endif
/* Make cerain my local apic is useable */
enable_lapic();
-
- nodeid = lapicid() & 0xf;
-
- /* Is this a cpu only reset? */
- if (cpu_init_detected(nodeid)) {
+
+#if CONFIG_LOGICAL_CPUS==1
+ id = get_node_core_id_x();
+ /* Is this a cpu only reset? */
+ if (cpu_init_detected(id.nodeid)) {
+#else
+ nodeid = lapicid();
+ /* Is this a cpu only reset? */
+ if (cpu_init_detected(nodeid)) {
+#endif
if (last_boot_normal()) {
goto normal_image;
} else {
@@ -35,7 +49,6 @@ static unsigned long main(unsigned long bist)
goto fallback_image;
}
}
-
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
diff --git a/src/mainboard/tyan/s2882/mptable.c b/src/mainboard/tyan/s2882/mptable.c
index 4bf298923d..a331247fa9 100644
--- a/src/mainboard/tyan/s2882/mptable.c
+++ b/src/mainboard/tyan/s2882/mptable.c
@@ -4,6 +4,9 @@
#include <device/pci_ids.h>
#include <string.h>
#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#endif
#define ASSIGN_IRQ 0
@@ -19,8 +22,12 @@ void *smp_write_config_table(void *v)
unsigned char bus_8131_1;
unsigned char bus_8131_2;
unsigned char bus_8111_1;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ unsigned apicid_base;
+ unsigned apicid_8111;
+ unsigned apicid_8131_1;
+ unsigned apicid_8131_2;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
memset(mc, 0, sizeof(*mc));
memcpy(mc->mpc_signature, sig, sizeof(sig));
@@ -86,7 +93,16 @@ void *smp_write_config_table(void *v)
/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
+#if CONFIG_LOGICAL_CPUS==1
+ apicid_base = get_apicid_base(3);
+#else
+ apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+ apicid_8111 = apicid_base+0;
+ apicid_8131_1 = apicid_base+1;
+ apicid_8131_2 = apicid_base+2;
+
+ smp_write_ioapic(mc, apicid_8111, 0x11, 0xfec00000);
{
device_t dev;
struct resource *res;
@@ -94,35 +110,35 @@ void *smp_write_config_table(void *v)
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_1, 0x11, res->base);
}
}
dev = dev_find_slot(1, PCI_DEVFN(0x2,1));
if (dev) {
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (res) {
- smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ smp_write_ioapic(mc, apicid_8131_2, 0x11, res->base);
}
}
}
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x2, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x2, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x2, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x2, 0x6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x2, 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x2, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x2, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x2, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf);
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, apicid_8111, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, apicid_8111, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, apicid_8111, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, apicid_8111, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, apicid_8111, 0x6);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, apicid_8111, 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, apicid_8111, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, apicid_8111, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, apicid_8111, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, apicid_8111, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, apicid_8111, 0xf);
#if ASSIGN_IRQ
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (4<<2)|3, 0x2, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (4<<2)|3, apicid_8111, 0x13);
{
device_t dev;
@@ -148,7 +164,7 @@ void *smp_write_config_table(void *v)
#endif
//On Board AMD USB
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x2, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, apicid_8111, 0x13);
#if ASSIGN_IRQ
printk_info("setting Onboard AMD USB \n");
@@ -157,7 +173,7 @@ void *smp_write_config_table(void *v)
#endif
//On Board ATI Display Adapter
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, 0x2, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (6<<2)|0, apicid_8111, 0x12);
#if ASSIGN_IRQ
printk_info("setting Onboard ATI Display Adapter\n");
@@ -167,10 +183,10 @@ void *smp_write_config_table(void *v)
#if 1
//Slot 5 PCI 32
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, 0x2, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, 0x2, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, 0x2, 0x12); //
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, 0x2, 0x13); //
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|0, apicid_8111, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|1, apicid_8111, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|2, apicid_8111, 0x12); //
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (4<<2)|3, apicid_8111, 0x13); //
#if ASSIGN_IRQ
printk_info("setting Slot 5 \n");
@@ -180,7 +196,7 @@ void *smp_write_config_table(void *v)
#endif
//Onboard SI Serial ATA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, 0x2, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (5<<2)|0, apicid_8111, 0x13);
#if ASSIGN_IRQ
printk_info("setting Onboard SI Serail ATA\n");
@@ -189,7 +205,7 @@ void *smp_write_config_table(void *v)
#endif
//Onboard Intel 82551 10/100M NIC
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, 0x2, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (8<<2)|0, apicid_8111, 0x12);
#if ASSIGN_IRQ
printk_info("setting Onboard Intel NIC\n");
@@ -199,10 +215,10 @@ void *smp_write_config_table(void *v)
#if 1
//Slot 3 PCIX 100/66
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, 0x3, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, 0x3, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, 0x3, 0x1);//
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, 0x3, 0x2);//
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|0, apicid_8131_1, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|1, apicid_8131_1, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|2, apicid_8131_1, 0x1);//
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (3<<2)|3, apicid_8131_1, 0x2);//
#if ASSIGN_IRQ
printk_info("setting Slot 3\n");
@@ -211,10 +227,10 @@ void *smp_write_config_table(void *v)
#endif
//Slot 4 PCIX 100/66
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, 0x3, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, 0x3, 0x3);//
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, 0x3, 0x0);//
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, 0x3, 0x1);//
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|0, apicid_8131_1, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|1, apicid_8131_1, 0x3);//
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|2, apicid_8131_1, 0x0);//
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (2<<2)|3, apicid_8131_1, 0x1);//
#if ASSIGN_IRQ
printk_info("setting Slot 4\n");
@@ -224,8 +240,8 @@ void *smp_write_config_table(void *v)
#endif
//Onboard adaptec scsi
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|0, 0x3, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, 0x3, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|0, apicid_8131_1, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (6<<2)|1, apicid_8131_1, 0x1);
#if ASSIGN_IRQ
printk_info("setting Onboard Adaptec SCSI\n");
@@ -234,8 +250,8 @@ void *smp_write_config_table(void *v)
#endif
//On Board NIC
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, 0x3, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, 0x3, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, apicid_8131_1, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, apicid_8131_1, 0x1);
#if ASSIGN_IRQ
@@ -246,10 +262,10 @@ void *smp_write_config_table(void *v)
#if 1
//Slot 1 PCI-X 133/100/66
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, 0x4, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, 0x4, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, 0x4, 0x2); //
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, 0x4, 0x3); //
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, apicid_8131_2, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, apicid_8131_2, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, apicid_8131_2, 0x2); //
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, apicid_8131_2, 0x3); //
#if ASSIGN_IRQ
printk_info("setting Slot 1\n");
@@ -258,10 +274,10 @@ void *smp_write_config_table(void *v)
#endif
//Slot 2 PCI-X 133/100/66
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, 0x4, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, 0x4, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, 0x4, 0x3);//
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, 0x4, 0x0);//
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|0, apicid_8131_2, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|1, apicid_8131_2, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|2, apicid_8131_2, 0x3);//
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (1<<2)|3, apicid_8131_2, 0x0);//
#if ASSIGN_IRQ
printk_info("setting Slot 2\n");