eric patch

        1. x86_setup_mtrr take address bit.
        2. generic ht, pcix, pcie beidge...
        3. scan bus and reset_bus
        4. ht read ctrl to decide if the ht chain
           is ready
        5. Intel e7520 and e7525 support
        6. new ich5r support
        7. intel sb 6300 support.

yhlu patch
	1. split x86_setup_mtrrs to fixed and var
	2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
	3. in_conherent.c K8_SCAN_PCI_BUS


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 151 insertions, 357 deletions

diff --git a/src/mainboard/tyan/s2882/Config.lb b/src/mainboard/tyan/s2882/Config.lb
index 7739a67ca6..6f71a49864 100644
--- a/src/mainboard/tyan/s2882/Config.lb
+++ b/src/mainboard/tyan/s2882/Config.lb
@@ -44,7 +44,7 @@ driver mainboard.o
 
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-#object reset.o
+object reset.o
 
 if USE_DCACHE_RAM
 
@@ -278,36 +278,37 @@ chip northbridge/amd/amdk8/root_complex
 					end
 					device pci 1.1 on end
 					device pci 1.2 on end
-                                        device pci 1.3 on 
-#                                                chip drivers/generic/generic #dimm 0-0-0
-#                                                        device i2c 50 on end
-#                                                end
-#                                                chip drivers/generic/generic #dimm 0-0-1
-#                                                        device i2c 51 on end
-#                                                end     
-#                                                chip drivers/generic/generic #dimm 0-1-0
-#                                                        device i2c 52 on end
-#                                                end
-#                                                chip drivers/generic/generic #dimm 0-1-1
-#                                                        device i2c 53 on end
-#                                                end
-#                                                chip drivers/generic/generic #dimm 1-0-0
-#                                                        device i2c 54 on end
-#                                                end
-#                                                chip drivers/generic/generic #dimm 1-0-1
-#                                                        device i2c 55 on end
-#                                                end
-#                                                chip drivers/generic/generic #dimm 1-1-0
-#                                                        device i2c 56 on end
-#                                                end
-#                                                chip drivers/generic/generic #dimm 1-1-1
-#                                                        device i2c 57 on end
-#                                                end
+					device pci 1.3 on end
+					device pci 1.3 on 
+#						 chip drivers/generic/generic #dimm 0-0-0
+#							 device i2c 50 on end
+#						 end
+#						 chip drivers/generic/generic #dimm 0-0-1
+#							 device i2c 51 on end
+#						 end	 
+#						 chip drivers/generic/generic #dimm 0-1-0
+#							 device i2c 52 on end
+#						 end
+#						 chip drivers/generic/generic #dimm 0-1-1
+#							 device i2c 53 on end
+#						 end
+#						 chip drivers/generic/generic #dimm 1-0-0
+#							 device i2c 54 on end
+#						 end
+#						 chip drivers/generic/generic #dimm 1-0-1
+#							 device i2c 55 on end
+#						 end
+#						 chip drivers/generic/generic #dimm 1-1-0
+#							 device i2c 56 on end
+#						 end
+#						 chip drivers/generic/generic #dimm 1-1-1
+#							 device i2c 57 on end
+#						 end
                                         end # acpi
 					device pci 1.5 off end
 					device pci 1.6 off end
-                                        register "ide0_enable" = "1"
-                                        register "ide1_enable" = "1"
+					register "ide0_enable" = "1"
+					register "ide1_enable" = "1"
 				end
 			end #  device pci 18.0 
 			
diff --git a/src/mainboard/tyan/s2882/Options.lb b/src/mainboard/tyan/s2882/Options.lb
index 1249719210..ffa34c4f08 100644
--- a/src/mainboard/tyan/s2882/Options.lb
+++ b/src/mainboard/tyan/s2882/Options.lb
@@ -3,9 +3,6 @@ uses HAVE_PIRQ_TABLE
 uses USE_FALLBACK_IMAGE
 uses HAVE_FALLBACK_BOOT
 uses HAVE_HARD_RESET
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
 uses IRQ_SLOT_COUNT
 uses HAVE_OPTION_TABLE
 uses CONFIG_MAX_CPUS
@@ -87,13 +84,6 @@ default HAVE_FALLBACK_BOOT=1
 default HAVE_HARD_RESET=1
 
 ##
-## Funky hard reset implementation
-## 
-default HARD_RESET_BUS=1
-default HARD_RESET_DEVICE=4
-default HARD_RESET_FUNCTION=0
-
-##
 ## Build code to export a programmable irq routing table
 ##
 default HAVE_PIRQ_TABLE=1
@@ -153,7 +143,7 @@ default CONFIG_IOAPIC=1
 ##
 ## Clean up the motherboard id strings
 ##
-default MAINBOARD_PART_NUMBER="s2882"
+default MAINBOARD_PART_NUMBER="S2882"
 default MAINBOARD_VENDOR="Tyan"
 default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1
 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2882
diff --git a/src/mainboard/tyan/s2882/auto.c b/src/mainboard/tyan/s2882/auto.c
index fb7a63abb5..910db9e8a5 100644
--- a/src/mainboard/tyan/s2882/auto.c
+++ b/src/mainboard/tyan/s2882/auto.c
@@ -27,20 +27,52 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
+/* Look up a which bus a given node/link combination is on.
+ * return 0 when we can't find the answer.
+ */
+static unsigned node_link_to_bus(unsigned node, unsigned link)
+{
+        unsigned reg;
+        
+        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+                unsigned config_map;
+                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
+                if ((config_map & 3) != 3) {
+                        continue; 
+                }       
+                if ((((config_map >> 4) & 7) == node) &&
+                        (((config_map >> 8) & 3) == link))
+                {       
+                        return (config_map >> 16) & 0xff;
+                }       
+        }       
+        return 0;
+}       
+
 static void hard_reset(void)
 {
+        device_t dev;
+
+        /* Find the device */
+        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
+
         set_bios_reset();
-        
+
         /* enable cf9 */
-        pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+        pci_write_config8(dev, 0x41, 0xf1);
         /* reset */
         outb(0x0e, 0x0cf9);
 }
 
 static void soft_reset(void)
 {
+        device_t dev;
+
+        /* Find the device */
+        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
+
         set_bios_reset();
-        pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+        pci_write_config8(dev, 0x47, 1);
 }
 
 #define REV_B_RESET 0
@@ -64,7 +96,6 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
    }
 }
 
-
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
 {
         /* nothing to do */
@@ -160,7 +191,7 @@ static void main(unsigned long bist)
                         || (id.coreid != 0)
 #endif
                 ) {
-                        stop_this_cpu(); 
+                        stop_this_cpu(); // it will stop all cores except core0 of cpu0
                 }
         }
 
@@ -176,7 +207,6 @@ static void main(unsigned long bist)
 #if CONFIG_LOGICAL_CPUS==1
         start_other_cores();
 #endif
-        // automatically set that for you, but you might meet tight space
         needs_reset |= ht_setup_chains_x();
         if (needs_reset) {
                 print_info("ht reset -\r\n");
diff --git a/src/mainboard/tyan/s2882/cache_as_ram_auto.c b/src/mainboard/tyan/s2882/cache_as_ram_auto.c
index 1b3d77a206..f0adb4204b 100644
--- a/src/mainboard/tyan/s2882/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2882/cache_as_ram_auto.c
@@ -36,21 +36,52 @@
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+/* Look up a which bus a given node/link combination is on.
+ * return 0 when we can't find the answer.
+ */
+static unsigned node_link_to_bus(unsigned node, unsigned link)
+{
+        unsigned reg;
+        
+        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
+                unsigned config_map;
+                config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg);
+                if ((config_map & 3) != 3) {
+                        continue; 
+                }       
+                if ((((config_map >> 4) & 7) == node) &&
+                        (((config_map >> 8) & 3) == link))
+                {       
+                        return (config_map >> 16) & 0xff;
+                }       
+        }       
+        return 0;
+}       
 
 static void hard_reset(void)
 {
+        device_t dev;
+
+        /* Find the device */
+        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 3);
+
         set_bios_reset();
 
         /* enable cf9 */
-        pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+        pci_write_config8(dev, 0x41, 0xf1);
         /* reset */
         outb(0x0e, 0x0cf9);
 }
 
 static void soft_reset(void)
 {
+        device_t dev;
+
+        /* Find the device */
+        dev = PCI_DEV(node_link_to_bus(0, 0), 0x04, 0);
+
         set_bios_reset();
-        pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+        pci_write_config8(dev, 0x47, 1);
 }
 
 static void memreset_setup(void)
@@ -93,6 +124,8 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #if CONFIG_LOGICAL_CPUS==1
 #define SET_NB_CFG_54 1
 #include "cpu/amd/dualcore/dualcore.c"
+#else
+#include "cpu/amd/model_fxx/node_id.c"
 #endif
 
 #define FIRST_CPU  1
@@ -236,6 +269,7 @@ void amd64_main(unsigned long bist)
 #if CONFIG_LOGICAL_CPUS==1
                 if(id.coreid == 0) {
                         if (cpu_init_detected(id.nodeid)) {
+//                                __asm__ volatile ("jmp __cpu_reset");
 				cpu_reset = 1;
 				goto cpu_reset_x;
                         }
@@ -249,7 +283,6 @@ void amd64_main(unsigned long bist)
                 distinguish_cpu_resets(nodeid);
 #endif
 
-
                 if (!boot_cpu()
 #if CONFIG_LOGICAL_CPUS==1 
                         || (id.coreid != 0)
@@ -261,7 +294,6 @@ void amd64_main(unsigned long bist)
                 }
         }
 
-	
  	w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
@@ -270,14 +302,11 @@ void amd64_main(unsigned long bist)
 	report_bist_failure(bist);
 
         setup_default_resource_map();
-#if 0
-        dump_pci_device(PCI_DEV(0, 0x18, 0));
-	dump_pci_device(PCI_DEV(0, 0x19, 0));
-#endif
 
 	needs_reset = setup_coherent_ht_domain();
 	
 #if CONFIG_LOGICAL_CPUS==1
+        // It is said that we should start core1 after all core0 launched
         start_other_cores();
 #endif
         needs_reset |= ht_setup_chains_x();
@@ -288,21 +317,10 @@ void amd64_main(unsigned long bist)
        	}
 
 	enable_smbus();
-#if 0
-	dump_spd_registers(&cpu[0]);
-#endif
-#if 0
-	dump_smbus_registers();
-#endif
 
 	memreset_setup();
 	sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
 
-#if 0
-	dump_pci_devices();
-#endif
-
-
 #if 1
         {
         /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */
@@ -319,6 +337,7 @@ void amd64_main(unsigned long bist)
         }
 #endif
 
+#if 1
 
 
 cpu_reset_x:
@@ -382,6 +401,7 @@ cpu_reset_x:
 		copy_and_run(new_cpu_reset);
 		/* We will not return */
 	}
+#endif
 
 
 	print_debug("should not be here -\r\n");
diff --git a/src/mainboard/tyan/s2882/irq_tables.c b/src/mainboard/tyan/s2882/irq_tables.c
index cdff230a2f..add22b4e03 100644
--- a/src/mainboard/tyan/s2882/irq_tables.c
+++ b/src/mainboard/tyan/s2882/irq_tables.c
@@ -1,301 +1,48 @@
-/* This file was generated by getpir.c, do not modify! 
-   (but if you do, please run checkpir on it to verify)
-   Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
-
-   Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
 #include <arch/pirq_routing.h>
+#include <device/pci.h>
 
-const struct irq_routing_table intel_irq_routing_table = {
-        PIRQ_SIGNATURE, /* u32 signature */
-        PIRQ_VERSION,   /* u16 version   */
-        32+16*15,        /* there can be total 15 devices on the bus */
-        1,           /* Where the interrupt router lies (bus) */
-        (4<<3)|3,           /* Where the interrupt router lies (dev) */
-        0,         /* IRQs devoted exclusively to PCI usage */
-        0x1022,         /* Vendor */
-        0x746b,         /* Device */
-        0,         /* Crap (miniport) */
-        { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
-        0xff,         /*  u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structu
-re (including checksum) */
-        {
-                {1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
-                {0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
-                {0x4,(6<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
-                {0x3,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
-                {0x3,(1<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
-                {0x2,(3<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
-                {0x2,(2<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
-                {0x4,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
-                {0x4,(5<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
-                {0x4,(8<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
-                {0x2,(6<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
-                {0x2,(5<<3)|0, {{0x3, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}}, 0, 0},
-                {0x2,(9<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
-                {0x3,(4<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
-                {0x3,(5<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x7, 0},
-        }
-};
-
-static unsigned node_link_to_bus(unsigned node, unsigned link)
-{
-        device_t dev;
-        unsigned reg;
+#define IRQ_ROUTER_BUS		1
+#define IRQ_ROUTER_DEVFN	PCI_DEVFN(4,3)
+#define IRQ_ROUTER_VENDOR	0x1022
+#define IRQ_ROUTER_DEVICE	0x746b
 
-        dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
-        if (!dev) {
-                return 0;
-        }
-        for(reg = 0xE0; reg < 0xF0; reg += 0x04) {
-                uint32_t config_map;
-                unsigned dst_node;
-                unsigned dst_link;
-                unsigned bus_base;
-                config_map = pci_read_config32(dev, reg);
-                if ((config_map & 3) != 3) {
-                        continue;
-                }
-                dst_node = (config_map >> 4) & 7;
-                dst_link = (config_map >> 8) & 3;
-                bus_base = (config_map >> 16) & 0xff;
-#if 0                           
-                printk_debug("node.link=bus: %d.%d=%d 0x%2x->0x%08x\n",
-                        dst_node, dst_link, bus_base,
-                        reg, config_map);
-#endif
-                if ((dst_node == node) && (dst_link == link))
-                {
-                        return bus_base;
-                }
-        }
-        return 0;
-}
+#define AVAILABLE_IRQS 0xdef8
+#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
+	{ bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
+	{linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
 
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, 
-		uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
-		uint8_t slot, uint8_t rfu)
-{
-        pirq_info->bus = bus; 
-        pirq_info->devfn = devfn;
-                pirq_info->irq[0].link = link0;
-                pirq_info->irq[0].bitmap = bitmap0;
-                pirq_info->irq[1].link = link1;
-                pirq_info->irq[1].bitmap = bitmap1;
-                pirq_info->irq[2].link = link2;
-                pirq_info->irq[2].bitmap = bitmap2;
-                pirq_info->irq[3].link = link3;
-                pirq_info->irq[3].bitmap = bitmap3;
-        pirq_info->slot = slot;
-        pirq_info->rfu = rfu;
-}
+/*  Each IRQ_SLOT entry consists of:
+ *  bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu  
+ */
 
+const struct irq_routing_table intel_irq_routing_table = {
+	PIRQ_SIGNATURE,		/* u32 signature */
+	PIRQ_VERSION,           /* u16 version   */
+	32+16*IRQ_SLOT_COUNT,	/* there can be total IRQ_SLOT_COUNT table entries */
+	IRQ_ROUTER_BUS,		/* Where the interrupt router lies (bus) */
+	IRQ_ROUTER_DEVFN,	/* Where the interrupt router lies (dev) */
+	0x00,			/* IRQs devoted exclusively to PCI usage */
+	IRQ_ROUTER_VENDOR,	/* Vendor */
+	IRQ_ROUTER_DEVICE,	/* Device */
+	0x00,			/* Crap (miniport) */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	0xb0,           /*  u8 checksum , mod 256 checksum must give zero */
+	{	/* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
+		/* PCI Slot 1-6 */
+		IRQ_SLOT(1, 3,1,0, 2,3,4,1 ),
+		IRQ_SLOT(2, 3,2,0, 3,4,1,2 ),
+		IRQ_SLOT(3, 2,1,0, 2,3,4,1 ),
+		IRQ_SLOT(4, 2,2,0, 3,4,1,2 ),
+		IRQ_SLOT(5, 4,5,0, 2,3,4,1 ),
+		IRQ_SLOT(6, 4,4,0, 1,2,3,4 ),
+		/* Onboard NICs */
+		IRQ_SLOT(0, 2,3,0, 4,0,0,0 ),
+		IRQ_SLOT(0, 2,4,0, 4,0,0,0 ),
+		/* Let Linux know about bus 1 */
+		IRQ_SLOT(0, 1,4,3, 0,0,0,0 ),
+	}
+};
 unsigned long write_pirq_routing_table(unsigned long addr)
 {
-
-	struct irq_routing_table *pirq;
-	struct irq_info *pirq_info;
-	unsigned slot_num;
-	uint8_t *v;
-
-        uint8_t sum=0;
-        int i;
-
-        unsigned char bus_chain_0;
-        unsigned char bus_8131_1;
-        unsigned char bus_8131_2;
-        unsigned char bus_8111_1;
-        {
-                device_t dev;
-
-                /* HT chain 0 */
-                bus_chain_0 = node_link_to_bus(0, 0);
-                if (bus_chain_0 == 0) {
-                        printk_debug("ERROR - cound not find bus for node 0 chain 0, using defaults\n");
-                        bus_chain_0 = 1;
-                }
-
-                /* 8111 */
-                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
-                if (dev) {
-                        bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
-
-                        bus_8111_1 = 4;
-                }
-                /* 8131-1 */
-                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
-                if (dev) {
-                        bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
-
-                        bus_8131_1 = 2;
-                }
-                /* 8131-2 */
-                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
-                if (dev) {
-                        bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
-                }
-                else {
-                        printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
-
-                        bus_8131_2 = 3;
-                }
-        }
-
-        /* Align the table to be 16 byte aligned. */
-        addr += 15;
-        addr &= ~15;
-
-        /* This table must be betweeen 0xf0000 & 0x100000 */
-        printk_info("Writing IRQ routing tables to 0x%x...", addr);
-
-	pirq = (void *)(addr);
-	v = (uint8_t *)(addr);
-	
-	pirq->signature = PIRQ_SIGNATURE;
-	pirq->version  = PIRQ_VERSION;
-	
-	pirq->rtr_bus = bus_chain_0;
-	pirq->rtr_devfn = (4<<3)|3;
-
-	pirq->exclusive_irqs = 0;
-	
-	pirq->rtr_vendor = 0x1022;
-	pirq->rtr_device = 0x746b;
-
-	pirq->miniport_data = 0;
-
-	memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
-	pirq_info = (void *) ( &pirq->checksum + 1);
-	slot_num = 0;
-
-        {
-                device_t dev;
-                dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x04,3));
-                if (dev) {
-                        /* initialize PCI interupts - these assignments depend
-                        on the PCB routing of PINTA-D 
-
-                        PINTA = IRQ5
-                        PINTB = IRQ9
-                        PINTC = IRQ11
-                        PINTD = IRQ10
-                        */
-                        pci_write_config16(dev, 0x56, 0xab95);
-                }
-        }
-
-        printk_info("setting Onboard AMD Southbridge \n");
-        static const unsigned char slotIrqs_1_4[4] = { 5, 9, 11, 10 };
-        pci_assign_irqs(bus_chain_0, 4, slotIrqs_1_4);
-        write_pirq_info(pirq_info, bus_chain_0,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-	pirq_info++; slot_num++;
-	
-        printk_info("setting Onboard AMD USB \n");
-        static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 10 };
-        pci_assign_irqs(bus_8111_1, 0, slotIrqs_8111_1_0);
-        write_pirq_info(pirq_info, bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
-	pirq_info++; slot_num++;
-
-        printk_info("setting Onboard ATI Display Adapter\n");
-        static const unsigned char slotIrqs_8111_1_6[4] = { 11, 0, 0, 0 };
-        pci_assign_irqs(bus_8111_1, 6, slotIrqs_8111_1_6);
-        write_pirq_info(pirq_info, bus_8111_1,(6<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-
-        printk_info("setting Slot 1\n");
-        static const unsigned char slotIrqs_8131_2_3[4] = { 5, 9, 11, 10 };
-        pci_assign_irqs(bus_8131_2, 3, slotIrqs_8131_2_3);
-        write_pirq_info(pirq_info, bus_8131_2,(3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0);
-	pirq_info++; slot_num++;
-
-        printk_info("setting Slot 2\n");
-        static const unsigned char slotIrqs_8131_2_1[4] = { 9, 11, 10, 5 };
-        pci_assign_irqs(bus_8131_2, 1, slotIrqs_8131_2_1);
-        write_pirq_info(pirq_info, bus_8131_2,(1<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0);
-	pirq_info++; slot_num++;
-
-        printk_info("setting Slot 3\n");
-        static const unsigned char slotIrqs_8131_1_3[4] = { 10, 5, 9, 11 };
-        pci_assign_irqs(bus_8131_1, 3, slotIrqs_8131_1_3);
-        write_pirq_info(pirq_info, bus_8131_1,(3<<3)|0, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x3, 0);
-	pirq_info++; slot_num++;
-
-        printk_info("setting Slot 4\n");
-        static const unsigned char slotIrqs_8131_1_2[4] = { 11, 10, 5, 9 };
-        pci_assign_irqs(bus_8131_1, 2, slotIrqs_8131_1_2);
-        write_pirq_info(pirq_info, bus_8131_1,(2<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x4, 0);
-	pirq_info++; slot_num++;
-
-        printk_info("setting Slot 5 \n");
-        static const unsigned char slotIrqs_8111_1_4[4] = { 5, 9, 11, 10 };
-        pci_assign_irqs(bus_8111_1, 4, slotIrqs_8111_1_4);
-        write_pirq_info(pirq_info, bus_8111_1,(4<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x5, 0);
-	pirq_info++; slot_num++;
-
-        printk_info("setting Onboard SI Serail ATA\n");
-        static const unsigned char slotIrqs_8111_1_5[4] = { 10, 0, 0, 0 };
-        pci_assign_irqs(bus_8111_1, 5, slotIrqs_8111_1_5);
-        write_pirq_info(pirq_info, bus_8111_1,(5<<3)|0, 0x4, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-
-        printk_info("setting Onboard Intel NIC\n");
-        static const unsigned char slotIrqs_8111_1_8[4] = { 11, 0, 0, 0 };
-        pci_assign_irqs(bus_8111_1, 8, slotIrqs_8111_1_8);
-        write_pirq_info(pirq_info, bus_8111_1,(8<<3)|0, 0x3, 0xdef8, 0, 0, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-
-        printk_info("setting Onboard Adaptec  SCSI\n");
-        static const unsigned char slotIrqs_8131_1_6[4] = { 5, 9, 0, 0 };
-        pci_assign_irqs(bus_8131_1, 6, slotIrqs_8131_1_6);
-        write_pirq_info(pirq_info, bus_8131_1,(6<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-#if 0
-	//??
-        write_pirq_info(pirq_info, bus_8131_1,(5<<3)|0, 0x3, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-#endif
-
-        printk_info("setting Onboard Broadcom NIC\n");
-        static const unsigned char slotIrqs_8131_1_9[4] = { 5, 9, 0, 0 };
-        pci_assign_irqs(bus_8131_1, 9, slotIrqs_8131_1_9);
-        write_pirq_info(pirq_info, bus_8131_1,(9<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0, 0, 0, 0, 0, 0);
-	pirq_info++; slot_num++;
-#if 0
-	//?? what's this?
-        write_pirq_info(pirq_info, bus_8131_2,(4<<3)|0, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x6, 0);
-	pirq_info++; slot_num++;
-#endif
-
-#if 0	
-	//?? what's this?
-        write_pirq_info(pirq_info, bus_8131_2,(5<<3)|0, 0x3, 0xdef8, 0x4, 0xdef8, 0x1, 0xdef8, 0x2, 0xdef8, 0x7, 0);
-	pirq_info++; slot_num++;
-#endif
-                
-	pirq->size = 32 + 16 * slot_num; 
-
-        for (i = 0; i < pirq->size; i++)
-                sum += v[i];	
-
-	sum = pirq->checksum - sum;
-
-        if (sum != pirq->checksum) {
-                pirq->checksum = sum;
-        }
-
-	return	(unsigned long) pirq_info;
-
+        return copy_pirq_routing_table(addr);
 }
diff --git a/src/mainboard/tyan/s2882/reset.c b/src/mainboard/tyan/s2882/reset.c
new file mode 100644
index 0000000000..3db3956ec6
--- /dev/null
+++ b/src/mainboard/tyan/s2882/reset.c
@@ -0,0 +1,6 @@
+#include "../../../southbridge/amd/amd8111/amd8111_reset.c"
+
+void hard_reset(void)
+{
+	amd8111_hard_reset(0, 0);
+}