summaryrefslogtreecommitdiff
path: root/src/mainboard/tyan/s2885/Options.lb
diff options
context:
space:
mode:
authorStefan Reinauer <stepan@openbios.org>2005-12-01 10:54:44 +0000
committerStefan Reinauer <stepan@openbios.org>2005-12-01 10:54:44 +0000
commit806e146e754a44f96c693cde707065b14f80d8a2 (patch)
treee8e174faffc6f7674b93b5b34d17ef3fa716c32f /src/mainboard/tyan/s2885/Options.lb
parent70597f96c45e225a42f395cdf16b4ad62459dc3b (diff)
downloadcoreboot-806e146e754a44f96c693cde707065b14f80d8a2.tar.xz
Applying 11_26_car_tyan.diff from Yinghai Lu.
NOTE: This will break the tree so it can be fixed up later git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2115 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2885/Options.lb')
-rw-r--r--src/mainboard/tyan/s2885/Options.lb20
1 files changed, 15 insertions, 5 deletions
diff --git a/src/mainboard/tyan/s2885/Options.lb b/src/mainboard/tyan/s2885/Options.lb
index 99ae422e00..dcff37450f 100644
--- a/src/mainboard/tyan/s2885/Options.lb
+++ b/src/mainboard/tyan/s2885/Options.lb
@@ -52,13 +52,17 @@ uses OBJCOPY
uses CONFIG_CHIP_NAME
uses CONFIG_CONSOLE_VGA
uses CONFIG_PCI_ROM_RUN
-uses K8_E0_MEM_HOLE_SIZEK
+uses K8_HW_MEM_HOLE_SIZEK
uses USE_DCACHE_RAM
uses DCACHE_RAM_BASE
uses DCACHE_RAM_SIZE
uses CONFIG_USE_INIT
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
###
### Build options
###
@@ -71,7 +75,9 @@ default ROM_SIZE=524288
##
## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
##
-default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=131072
+#256K
+default FALLBACK_SIZE=0x40000
##
## Build code for the fallback boot
@@ -120,7 +126,7 @@ default CONFIG_LOGICAL_CPUS=1
default CONFIG_CHIP_NAME=1
#1G memory hole
-default K8_E0_MEM_HOLE_SIZEK=0x100000
+default K8_HW_MEM_HOLE_SIZEK=0x100000
#VGA Console
default CONFIG_CONSOLE_VGA=1
@@ -130,10 +136,14 @@ default CONFIG_PCI_ROM_RUN=1
##
## enable CACHE_AS_RAM specifics
##
-default USE_DCACHE_RAM=0
+default USE_DCACHE_RAM=1
default DCACHE_RAM_BASE=0xcf000
default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=0
+default CONFIG_USE_INIT=1
+
+default ENABLE_APIC_EXT_ID=1
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=0
##
## Build code to setup a generic IOAPIC