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authorEric Biederman <ebiederm@xmission.com>2004-11-05 07:26:56 +0000
committerEric Biederman <ebiederm@xmission.com>2004-11-05 07:26:56 +0000
commit41d0fa38af010fdb2f9456ae3f693b1cadcc6bd6 (patch)
treedb01fb79b6e6f98999dc167567f88f40ad2d26d9 /src/mainboard/tyan/s2885
parent8bd555297e9c8eb8b9a006812f7a64197acff583 (diff)
downloadcoreboot-41d0fa38af010fdb2f9456ae3f693b1cadcc6bd6.tar.xz
- Modify all of the Opteron motherboards to have a separate logical
chip for the amdk8/root_complex git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2885')
-rw-r--r--src/mainboard/tyan/s2885/Config.lb174
1 files changed, 88 insertions, 86 deletions
diff --git a/src/mainboard/tyan/s2885/Config.lb b/src/mainboard/tyan/s2885/Config.lb
index 3327b32e82..a07e068af5 100644
--- a/src/mainboard/tyan/s2885/Config.lb
+++ b/src/mainboard/tyan/s2885/Config.lb
@@ -128,101 +128,103 @@ dir /pc80
config chip.h
# sample config for tyan/s2885
-chip northbridge/amd/amdk8
+chip northbridge/amd/amdk8/root_complex
device pci_domain 0 on
- device pci 18.0 on # LDT0
- chip southbridge/amd/amd8151
- # the on/off keyword is mandatory
- device pci 0.0 on end
- device pci 1.0 on end
- end
- end
- device pci 18.0 on end # LDT1
- device pci 18.0 on # northbridge
- # devices on link 2, link 2 == LDT 2
- chip southbridge/amd/amd8131
- # the on/off keyword is mandatory
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on end
- device pci 1.1 on end
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # LDT0
+ chip southbridge/amd/amd8151
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 1.0 on end
+ end
end
- chip southbridge/amd/amd8111
- # this "device pci 0.0" is the parent the next one
- # PCI bridge
- device pci 0.0 on
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on # northbridge
+ # devices on link 2, link 2 == LDT 2
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
device pci 0.0 on end
device pci 0.1 on end
- device pci 0.2 off end
- device pci 1.0 off end
+ device pci 1.0 on end
+ device pci 1.1 on end
end
- device pci 1.0 on
- chip drivers/generic/debug
- device pnp 2.0 on end
- device pnp 2.1 off end
- device pnp 2.2 off end
- device pnp 2.3 on end
- end
- chip superio/winbond/w83627hf
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # CIR
- io 0x60 = 0x100
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip drivers/generic/debug
+ device pnp 2.0 on end
+ device pnp 2.1 off end
+ device pnp 2.2 off end
+ device pnp 2.3 on end
+ end
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x201
+ io 0x62 = 0x330
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
end
- device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x201
- io 0x62 = 0x330
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 on end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
end
- device pci 1.1 on end
- device pci 1.2 on end
- device pci 1.3 on end
- device pci 1.5 on end
- device pci 1.6 off end
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
+ end # device pci 18.0
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on
+# chip drivers/generic/debug
+# device pnp 1.0 on end
+# device pnp 1.1 off end
+# device pnp 1.2 off end
+# device pnp 1.3 on end
+# end
end
- end # device pci 18.0
-
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on
-# chip drivers/generic/debug
-# device pnp 1.0 on end
-# device pnp 1.1 off end
-# device pnp 1.2 off end
-# device pnp 1.3 on end
-# end
end
chip northbridge/amd/amdk8