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| author | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2011-04-20 20:54:07 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2011-04-20 20:54:07 +0000 |
| commit | 42fa7fe28b60b448f501e99ee285a0af12c86d34 (patch) | |
| tree | 247586f11a5be9dcbea2cbafaede92df058ac14b /src/mainboard/tyan/s2885 | |
| parent | d8129f92c0cbd6a561195c1628ba3f9f98eccd50 (diff) | |
| download | coreboot-42fa7fe28b60b448f501e99ee285a0af12c86d34.tar.xz | |
run uart_init() from console_init, just like the other console initialization functions.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2885')
| -rw-r--r-- | src/mainboard/tyan/s2885/romstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/tyan/s2885/romstage.c b/src/mainboard/tyan/s2885/romstage.c index 80f02db891..41743ae0c4 100644 --- a/src/mainboard/tyan/s2885/romstage.c +++ b/src/mainboard/tyan/s2885/romstage.c @@ -85,7 +85,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) bsp_apicid = init_cpus(cpu_init_detectedx); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); |