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| author | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:15:30 +0000 |
|---|---|---|
| committer | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:15:30 +0000 |
| commit | ef03afa405b049a172146aab93cfb81fb21f3945 (patch) | |
| tree | 3b59033be66edd60c2cc6c66d6875153dc052a72 /src/mainboard/tyan/s2891/mptable.c | |
| parent | 014c3e185fe8e1455e56efeb496715a67ce292bb (diff) | |
| download | coreboot-ef03afa405b049a172146aab93cfb81fb21f3945.tar.xz | |
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-34
Creator: Yinghai Lu <yhlu@tyan.com>
AMD D0/E0 Opteron new mem mapping support, AMD E Opteron mem hole support,AMD K8 Four Ranks DIMM support
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1950 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2891/mptable.c')
| -rw-r--r-- | src/mainboard/tyan/s2891/mptable.c | 21 |
1 files changed, 14 insertions, 7 deletions
diff --git a/src/mainboard/tyan/s2891/mptable.c b/src/mainboard/tyan/s2891/mptable.c index 9aa2f336b8..e8d5f4ccc9 100644 --- a/src/mainboard/tyan/s2891/mptable.c +++ b/src/mainboard/tyan/s2891/mptable.c @@ -3,6 +3,9 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> +#if CONFIG_LOGICAL_CPUS==1 +#include <cpu/amd/dualcore.h> +#endif void *smp_write_config_table(void *v) { @@ -128,7 +131,11 @@ void *smp_write_config_table(void *v) smp_write_bus(mc, bus_isa, "ISA "); /*I/O APICs: APIC ID Version State Address*/ - apicid_base = CONFIG_MAX_CPUS; +#if CONFIG_LOGICAL_CPUS==1 + apicid_base = get_apicid_base(3); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif apicid_ck804 = apicid_base; apicid_8131_1 = apicid_base+1; apicid_8131_2 = apicid_base+2; @@ -149,12 +156,12 @@ void *smp_write_config_table(void *v) dword = 0x0000d218; pci_write_config32(dev, 0x7c, dword); - dword = 0x8d001a00; + dword = 0x12008a00; pci_write_config32(dev, 0x80, dword); - dword = 0x00000072; + dword = 0x0000007d; pci_write_config32(dev, 0x84, dword); @@ -193,13 +200,13 @@ void *smp_write_config_table(void *v) smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+1)<<2)|1, apicid_ck804, 0xa); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x16); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|0, apicid_ck804, 0x15); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x17); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE+2)<<2)|1, apicid_ck804, 0x14); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x14); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +7)<<2)|0, apicid_ck804, 0x17); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x15); + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_0, ((CK804_DEVN_BASE +8)<<2)|0, apicid_ck804, 0x16); #if 1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_ck804_5, (0x00<<2)|0, apicid_ck804, 0x12); // |