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| author | Ronald G. Minnich <rminnich@gmail.com> | 2005-11-23 21:01:08 +0000 |
|---|---|---|
| committer | Ronald G. Minnich <rminnich@gmail.com> | 2005-11-23 21:01:08 +0000 |
| commit | fb0a64ba77dbf1fa00d07453c76b875cd124cfcb (patch) | |
| tree | 43738db444fd43b8b29ebe9db5a685b8edbd8066 /src/mainboard/tyan/s2895/Options.lb | |
| parent | 872141a40291b73f061ae95a78baadb557efcd83 (diff) | |
| download | coreboot-fb0a64ba77dbf1fa00d07453c76b875cd124cfcb.tar.xz | |
CAR patch from YH LU
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2096 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2895/Options.lb')
| -rw-r--r-- | src/mainboard/tyan/s2895/Options.lb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb index 261b328781..fc63823480 100644 --- a/src/mainboard/tyan/s2895/Options.lb +++ b/src/mainboard/tyan/s2895/Options.lb @@ -136,10 +136,10 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=0 +default USE_DCACHE_RAM=1 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=0 +default CONFIG_USE_INIT=1 ## ## Build code to setup a generic IOAPIC |