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| author | Jason Schildt <jschildt@gmail.com> | 2005-10-25 21:50:06 +0000 |
|---|---|---|
| committer | Jason Schildt <jschildt@gmail.com> | 2005-10-25 21:50:06 +0000 |
| commit | 737253bf12b4903613233913621ff750cf74d398 (patch) | |
| tree | cb66da91b455f0e8c46225a6f838979c1d63c43a /src/mainboard/tyan/s2895 | |
| parent | f274d94360a8b5e80b688f5005a8e4a1da8bfe5f (diff) | |
| download | coreboot-737253bf12b4903613233913621ff750cf74d398.tar.xz | |
- See Issue Tracker id-15 "lnxi-patch-15".
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2895')
| -rw-r--r-- | src/mainboard/tyan/s2895/Options.lb | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb index fc63823480..261b328781 100644 --- a/src/mainboard/tyan/s2895/Options.lb +++ b/src/mainboard/tyan/s2895/Options.lb @@ -136,10 +136,10 @@ default CONFIG_PCI_ROM_RUN=1 ## ## enable CACHE_AS_RAM specifics ## -default USE_DCACHE_RAM=1 +default USE_DCACHE_RAM=0 default DCACHE_RAM_BASE=0xcf000 default DCACHE_RAM_SIZE=0x1000 -default CONFIG_USE_INIT=1 +default CONFIG_USE_INIT=0 ## ## Build code to setup a generic IOAPIC |