new cache_as_ram support

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 21 insertions, 24 deletions

diff --git a/src/mainboard/tyan/s2895/Options.lb b/src/mainboard/tyan/s2895/Options.lb
index 49b0e0b0de..c3f8ba3f8c 100644
--- a/src/mainboard/tyan/s2895/Options.lb
+++ b/src/mainboard/tyan/s2895/Options.lb
@@ -64,12 +64,17 @@ uses ENABLE_APIC_EXT_ID
 uses APIC_ID_OFFSET
 uses LIFT_BSP_APIC_ID
 
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+uses K8_SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
 ## ROM_SIZE is the size of boot ROM that this board will use.
 #512K bytes 
-default ROM_SIZE=524288
+#default ROM_SIZE=524288
 
 #1M bytes
-#default ROM_SIZE=1048576
+default ROM_SIZE=1048576
 
 ##
 ## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
@@ -134,6 +139,18 @@ default K8_HW_MEM_HOLE_SIZEK=0x100000
 #Opteron K8 1G HT Support
 default K8_HT_FREQ_1G_SUPPORT=1
 
+##HT Unit ID offset, default is 1, the typical one
+default HT_CHAIN_UNITID_BASE=0x0
+
+##real SB Unit ID, default is 0x20, mean dont touch it at last
+#default HT_CHAIN_END_UNITID_BASE=0x0
+
+#make the SB HT chain on bus 0, default is not (0)
+default K8_SB_HT_CHAIN_ON_BUS0=2
+
+##only offset for SB chain?, default is yes(1)
+default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
 #VGA
 default CONFIG_CONSOLE_VGA=1
 default CONFIG_PCI_ROM_RUN=1
@@ -144,7 +161,7 @@ default CONFIG_PCI_ROM_RUN=1
 default USE_DCACHE_RAM=1
 default DCACHE_RAM_BASE=0xcf000
 default DCACHE_RAM_SIZE=0x1000
-default CONFIG_USE_INIT=1
+default CONFIG_USE_INIT=0
 
 default ENABLE_APIC_EXT_ID=1
 default APIC_ID_OFFSET=0x10
diff --git a/src/mainboard/tyan/s2895/cache_as_ram_auto.c b/src/mainboard/tyan/s2895/cache_as_ram_auto.c
index 1ae0c9e5d1..00bf1a6c23 100644
--- a/src/mainboard/tyan/s2895/cache_as_ram_auto.c
+++ b/src/mainboard/tyan/s2895/cache_as_ram_auto.c
@@ -50,25 +50,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
 
-static void hard_reset(void)
-{
-        set_bios_reset();
-
-        /* full reset */
-	outb(0x0a, 0x0cf9);
-        outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
-        set_bios_reset();
-#if 1
-        /* link reset */
-	outb(0x02, 0x0cf9);
-        outb(0x06, 0x0cf9);
-#endif
-}
-
 static void memreset_setup(void)
 {
 }
@@ -239,7 +220,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	};
 
         int needs_reset;
-	unsigned cpu_reset = 0;
         unsigned bsp_apicid = 0;
 
         struct mem_controller ctrl[8];
@@ -288,5 +268,5 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	memreset_setup();
 	sdram_initialize(nodes, ctrl);
 
-	post_cache_as_ram(cpu_reset);
+	post_cache_as_ram();
 }