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authorMyles Watson <mylesgw@gmail.com>2009-10-06 20:36:34 +0000
committerMyles Watson <mylesgw@gmail.com>2009-10-06 20:36:34 +0000
commita3d6ea8a737193e217be5d7003d827da215a7bab (patch)
tree7475a7b08f56057748fe578adbcedd430e9eff84 /src/mainboard/tyan/s2895
parentc04be9322cd69b3340d78db84b7663848170fe94 (diff)
downloadcoreboot-a3d6ea8a737193e217be5d7003d827da215a7bab.tar.xz
Remove duplicate device trees for Tyan s289x. Remove pre-CBFS statements.
Signed-off-by: Myles Watson <mylesgw@gmail.com> Acked-by: Patrick Georgi <patrick.georgi@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s2895')
-rw-r--r--src/mainboard/tyan/s2895/Config.lb175
-rw-r--r--src/mainboard/tyan/s2895/devicetree.cb5
2 files changed, 2 insertions, 178 deletions
diff --git a/src/mainboard/tyan/s2895/Config.lb b/src/mainboard/tyan/s2895/Config.lb
index 9c6446eda6..911e279383 100644
--- a/src/mainboard/tyan/s2895/Config.lb
+++ b/src/mainboard/tyan/s2895/Config.lb
@@ -143,177 +143,4 @@ end
##
config chip.h
-# sample config for tyan/s2895
-chip northbridge/amd/amdk8/root_complex
- device apic_cluster 0 on
- chip cpu/amd/socket_940
- device apic 0 on end
- end
- end
- device pci_domain 0 on
- chip northbridge/amd/amdk8 #mc0
- device pci 18.0 on # northbridge
- # devices on link 0, link 0 == LDT 0
- chip southbridge/nvidia/ck804
- device pci 0.0 on end # HT
- device pci 1.0 on # LPC
- chip superio/smsc/lpc47b397
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.3 on # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 4
- end
- device pnp 2e.4 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.5 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.7 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.8 on # HW Monitor
- io 0x60 = 0x480
- chip drivers/generic/generic # LM95221 CPU temp
- device i2c 2b on end
- end
- chip drivers/generic/generic # EMCT03
- device i2c 54 on end
- end
- end
- device pnp 2e.a on # RT
- io 0x60 = 0x400
- end
- end
- end
- device pci 1.1 on # SM 0
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic #dimm 1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic #dimm 1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic #dimm 1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic #dimm 1-1-1
- device i2c 57 on end
- end
- end # SM
- device pci 1.1 on # SM 1
- chip drivers/generic/generic #MAC EEPROM
- device i2c 51 on end
- end
-
- end # SM
- device pci 2.0 on end # USB 1.1
- device pci 2.1 on end # USB 2
- device pci 4.0 on end # ACI
- device pci 4.1 off end # MCI
- device pci 6.0 on end # IDE
- device pci 7.0 on end # SATA 1
- device pci 8.0 on end # SATA 0
- device pci 9.0 on end # PCI
- device pci a.0 on end # NIC
- device pci b.0 off end # PCI E 3
- device pci c.0 off end # PCI E 2
- device pci d.0 off end # PCI E 1
- device pci e.0 on end # PCI E 0
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- register "sata0_enable" = "1"
- register "sata1_enable" = "1"
-# register "nic_rom_address" = "0xfff80000" # 64k
-# register "raid_rom_address" = "0xfff90000"
- register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
- register "mac_eeprom_addr" = "0x51"
- end
- end # device pci 18.0
- device pci 18.0 on end # Link 1
- device pci 18.0 on
- # devices on link 2, link 2 == LDT 2
- chip southbridge/amd/amd8131
- # the on/off keyword is mandatory
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on
- chip drivers/pci/onboard
- device pci 6.0 on end # lsi scsi
- device pci 6.1 on end
- end
- end
- device pci 1.1 on end
- end
- end # device pci 18.0
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end #mc0
-
- chip northbridge/amd/amdk8
- device pci 19.0 on # northbridge
- # devices on link 0, link 0 == LDT 0
- chip southbridge/nvidia/ck804
- device pci 0.0 on end # HT
- device pci 1.0 on end # LPC
- device pci 1.1 off end # SM
- device pci 2.0 off end # USB 1.1
- device pci 2.1 off end # USB 2
- device pci 4.0 off end # ACI
- device pci 4.1 off end # MCI
- device pci 6.0 off end # IDE
- device pci 7.0 off end # SATA 1
- device pci 8.0 off end # SATA 0
- device pci 9.0 off end # PCI
- device pci a.0 on end # NIC
- device pci b.0 off end # PCI E 3
- device pci c.0 off end # PCI E 2
- device pci d.0 off end # PCI E 1
- device pci e.0 on end # PCI E 0
-# register "nic_rom_address" = "0xfff80000" # 64k
- register "mac_eeprom_smbus" = "3"
- register "mac_eeprom_addr" = "0x51"
- end
- end # device pci 19.0
-
- device pci 19.0 on end
- device pci 19.0 on end
- device pci 19.1 on end
- device pci 19.2 on end
- device pci 19.3 on end
- end
- end # PCI domain
-
-# chip drivers/generic/debug
-# device pnp 0.0 off end # chip name
-# device pnp 0.1 off end # pci_regs_all
-# device pnp 0.2 off end # mem
-# device pnp 0.3 off end # cpuid
-# device pnp 0.4 on end # smbus_regs_all
-# device pnp 0.5 off end # dual core msr
-# device pnp 0.6 off end # cache size
-# device pnp 0.7 off end # tsc
-# end
-end # root_complex
+include devicetree.cb
diff --git a/src/mainboard/tyan/s2895/devicetree.cb b/src/mainboard/tyan/s2895/devicetree.cb
index 8ff77ee57e..6e4c2a63a1 100644
--- a/src/mainboard/tyan/s2895/devicetree.cb
+++ b/src/mainboard/tyan/s2895/devicetree.cb
@@ -91,7 +91,7 @@ chip northbridge/amd/amdk8/root_complex
device pci 8.0 on end # SATA 0
device pci 9.0 on end # PCI
device pci a.0 on end # NIC
- device pci b.0 off end # PCI E 3
+ device pci b.0 off end # PCI E 3
device pci c.0 off end # PCI E 2
device pci d.0 off end # PCI E 1
device pci e.0 on end # PCI E 0
@@ -99,8 +99,6 @@ chip northbridge/amd/amdk8/root_complex
register "ide1_enable" = "1"
register "sata0_enable" = "1"
register "sata1_enable" = "1"
-# register "nic_rom_address" = "0xfff80000" # 64k
-# register "raid_rom_address" = "0xfff90000"
register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1
register "mac_eeprom_addr" = "0x51"
end
@@ -146,7 +144,6 @@ chip northbridge/amd/amdk8/root_complex
device pci c.0 off end # PCI E 2
device pci d.0 off end # PCI E 1
device pci e.0 on end # PCI E 0
-# register "nic_rom_address" = "0xfff80000" # 64k
register "mac_eeprom_smbus" = "3"
register "mac_eeprom_addr" = "0x51"
end