summaryrefslogtreecommitdiff
path: root/src/mainboard/tyan/s2912
diff options
context:
space:
mode:
authorEdward O'Callaghan <eocallaghan@alterapraxis.com>2014-04-28 18:07:33 +1000
committerPatrick Georgi <patrick@georgi-clan.de>2014-04-30 19:06:47 +0200
commit81998090792ebc1a6e39455f5fcb4d2c9ec9c095 (patch)
tree214cb0402cdc6224b088a2a513f94719f0fd7405 /src/mainboard/tyan/s2912
parentf385ba42e340863df18555bf3cfffe70a96e2d8c (diff)
downloadcoreboot-81998090792ebc1a6e39455f5fcb4d2c9ec9c095.tar.xz
mainboard/: Avoid including early_serial.c from w83627hf
Following the reasoning of: dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5597 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/mainboard/tyan/s2912')
-rw-r--r--src/mainboard/tyan/s2912/romstage.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index e4a1c65a52..55cb95e7d0 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -36,8 +36,8 @@
#include "lib/delay.c"
#include "cpu/x86/lapic.h"
#include "northbridge/amd/amdk8/reset_test.c"
-#include "superio/winbond/w83627hf/early_serial.c"
-#include "superio/winbond/w83627hf/early_init.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
@@ -119,7 +119,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
setup_mb_resource_map();
console_init();