diff options
| author | Julius Werner <jwerner@chromium.org> | 2019-03-05 16:53:33 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-03-08 08:33:24 +0000 |
| commit | cd49cce7b70e80b4acc49b56bb2bb94370b4d867 (patch) | |
| tree | 8e89136e2da7cf54453ba8c112eda94415b56242 /src/mainboard/tyan/s2912_fam10 | |
| parent | b3a8cc54dbaf833c590a56f912209a5632b71f49 (diff) | |
| download | coreboot-cd49cce7b70e80b4acc49b56bb2bb94370b4d867.tar.xz | |
coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/tyan/s2912_fam10')
| -rw-r--r-- | src/mainboard/tyan/s2912_fam10/get_bus_conf.c | 2 | ||||
| -rw-r--r-- | src/mainboard/tyan/s2912_fam10/romstage.c | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c index 1cefda9285..f589ef6c8d 100644 --- a/src/mainboard/tyan/s2912_fam10/get_bus_conf.c +++ b/src/mainboard/tyan/s2912_fam10/get_bus_conf.c @@ -68,7 +68,7 @@ void get_bus_conf(void) } /*I/O APICs: APIC ID Version State Address*/ - if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) + if (CONFIG(LOGICAL_CPUS)) apicid_base = get_apicid_base(1); else apicid_base = CONFIG_MAX_PHYSICAL_CPUS; diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c index 084fc487fb..73951d18e2 100644 --- a/src/mainboard/tyan/s2912_fam10/romstage.c +++ b/src/mainboard/tyan/s2912_fam10/romstage.c @@ -170,7 +170,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if IS_ENABLED(CONFIG_LOGICAL_CPUS) +#if CONFIG(LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -180,7 +180,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); -#if IS_ENABLED(CONFIG_SET_FIDVID) +#if CONFIG(SET_FIDVID) msr = rdmsr(MSR_COFVID_STS); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); |