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author | arch import user (historical) <svn@openbios.org> | 2005-07-06 18:17:06 +0000 |
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committer | arch import user (historical) <svn@openbios.org> | 2005-07-06 18:17:06 +0000 |
commit | 7dec0f9ac33b1053de5045d6d72d6f882e0c782a (patch) | |
tree | c0f5a4593c581d4a86eaa620e2adbf4002a6350d /src/mainboard/tyan/s4880/failover.c | |
parent | 74d081a12c60a9a15f9ec7efde3cecef9732d0c9 (diff) | |
download | coreboot-7dec0f9ac33b1053de5045d6d72d6f882e0c782a.tar.xz |
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-56
Creator: Yinghai Lu <yhlu@tyan.com>
remove junk in s2885 cache_as_ram_auto.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1974 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s4880/failover.c')
-rw-r--r-- | src/mainboard/tyan/s4880/failover.c | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/src/mainboard/tyan/s4880/failover.c b/src/mainboard/tyan/s4880/failover.c new file mode 100644 index 0000000000..39758aefa7 --- /dev/null +++ b/src/mainboard/tyan/s4880/failover.c @@ -0,0 +1,88 @@ +#define ASSEMBLY 1 +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "pc80/mc146818rtc_early.c" +#include "southbridge/amd/amd8111/amd8111_enable_rom.c" +#include "northbridge/amd/amdk8/early_ht.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" + +#if CONFIG_LOGICAL_CPUS==1 +#include "cpu/amd/dualcore/dualcore_id.c" +#endif + + +static unsigned long main(unsigned long bist) +{ +#if CONFIG_LOGICAL_CPUS==1 + struct node_core_id id; +#else + unsigned nodeid; +#endif + /* Make cerain my local apic is useable */ + enable_lapic(); + +#if CONFIG_LOGICAL_CPUS==1 + id = get_node_core_id_x(); + /* Is this a cpu only reset? */ + if (cpu_init_detected(id.nodeid)) { +#else + nodeid = lapicid(); + /* Is this a cpu only reset? */ + if (cpu_init_detected(nodeid)) { +#endif + if (last_boot_normal()) { + goto normal_image; + } else { + goto cpu_reset; + } + } + /* Is this a secondary cpu? */ + if (!boot_cpu()) { + if (last_boot_normal()) { + goto normal_image; + } else { + goto fallback_image; + } + } + + + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* Setup the 8111 */ + amd8111_enable_rom(); + + /* Is this a deliberate reset by the bios */ + if (bios_reset_detected() && last_boot_normal()) { + goto normal_image; + } + /* This is the primary cpu how should I boot? */ + else if (do_normal_boot()) { + goto normal_image; + } + else { + goto fallback_image; + } + normal_image: + asm volatile ("jmp __normal_image" + : /* outputs */ + : "a" (bist) /* inputs */ + : /* clobbers */ + ); + cpu_reset: +#if 0 + asm volatile ("jmp __cpu_reset" + : /* outputs */ + : "a"(bist) /* inputs */ + : /* clobbers */ + ); +#endif + fallback_image: + return bist; +} |