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authorUwe Hermann <uwe@hermann-uwe.de>2010-11-21 17:29:59 +0000
committerUwe Hermann <uwe@hermann-uwe.de>2010-11-21 17:29:59 +0000
commit57b2ff886e0ce2c92820f5722c8031def3ac94cf (patch)
tree3bf95eb33cd3de0b8f2bae495b3ae1453601c4d3 /src/mainboard/tyan/s4880
parent5244e1ba63e5f3ea12066734bfb0d864a8f1f11d (diff)
downloadcoreboot-57b2ff886e0ce2c92820f5722c8031def3ac94cf.tar.xz
Drop excessive whitespace randomly sprinkled in romstage.c files.
Also drop some dead or useless code snippets. Abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6107 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan/s4880')
-rw-r--r--src/mainboard/tyan/s4880/romstage.c25
1 files changed, 6 insertions, 19 deletions
diff --git a/src/mainboard/tyan/s4880/romstage.c b/src/mainboard/tyan/s4880/romstage.c
index 157b14a3a6..09a052fc3c 100644
--- a/src/mainboard/tyan/s4880/romstage.c
+++ b/src/mainboard/tyan/s4880/romstage.c
@@ -9,28 +9,23 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -75,29 +70,22 @@ static inline int spd_read_byte(unsigned device, unsigned address)
return smbus_read_byte(device, address);
}
-
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
#define RC0 ((1<<2)<<8)
#define RC1 ((1<<1)<<8)
#define RC2 ((1<<4)<<8)
#define RC3 ((1<<3)<<8)
-#include "cpu/amd/car/post_cache_as_ram.c"
-
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const struct mem_controller cpu[] = {
@@ -192,4 +180,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_cache_as_ram();
}
-