Tyan S8226: Use SPD read code from F15 wrapper

Changes:
 - Get rid of the s8226 mainboard specific code and use the
   platform generic function wrapper that was added in change
   http://review.coreboot.org/#/c/2777/
   AMD Fam15: Add SPD read functions to wrapper code

 - Move DIMM addresses into devicetree.cb

Notes:
 - The DIMM reads only happen in romstage, so the function is not
   available in ramstage.  Point the read-SPD callback to a generic
   function in ramstage.
 - select_socket() and restore_socket() started by duplicating
   sp5100_set_gpio() and sp5100_restore_gpio(), which were in
   dimmSpd.c.  In addition to renaming the functions to more
   specifically state their purpose, some cleanup and magic number
   reduction was done.

Change-Id: I1eaf64986ef4fa3f89aed2b69d3f9c8c913f726f
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2827
Tested-by: build bot (Jenkins)
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 70 insertions, 3 deletions

diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c
index 1499d54792..8cb5b5c98c 100644
--- a/src/mainboard/tyan/s8226/BiosCallOuts.c
+++ b/src/mainboard/tyan/s8226/BiosCallOuts.c
@@ -23,6 +23,62 @@
 #include "Ids.h"
 #include "OptionsIds.h"
 #include "heapManager.h"
+#include <northbridge/amd/agesa/family15/dimmSpd.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#ifdef __PRE_RAM__
+/* These defines are used to select the appropriate socket for the SPD read
+ * because this is a multi-socket design.
+ */
+#define PCI_REG_GPIO_48_47_46_37_CNTRL   (0xA6)
+#define PCI_REG_GPIO_52_to_49_CNTRL      (0x50)
+#define GPIO_OUT_BIT_GPIO48              (BIT3)
+#define GPIO_OUT_BIT_GPIO49              (BIT0)
+#define GPIO_OUT_ENABLE_BIT_GPIO48       (BIT7)
+#define GPIO_OUT_ENABLE_BIT_GPIO49       (BIT4)
+
+static UINT8 select_socket(UINT8 socket_id)
+{
+	device_t sm_dev       = PCI_DEV(0, 0x14, 0); //SMBUS
+	UINT8    value        = 0;
+	UINT8    gpio52_to_49 = 0;
+
+	/* Configure GPIO49,48 to select the desired socket
+	 * GPIO49,48 control the IDTQS3253 S1,S0
+	 *  S1 S0 true table
+	 *   0  0   channel 0
+	 *   0  1   channel 1
+	 *   1  0   channel 2   -  Socket 0
+	 *   1  1   channel 3   -  Socket 1
+	 * Note: Above is abstracted from Schematic. But actually it seems to be other way.
+	 *   1  0   channel 2   -  Socket 1
+	 *   1  1   channel 3   -  Socket 0
+	 * Note: The DIMMs need to be plugged in from the farthest slot for each channel.
+	 */
+	gpio52_to_49 = pci_read_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL);
+	value  = gpio52_to_49 | GPIO_OUT_BIT_GPIO49; // Output of GPIO49 is always forced to "1"
+	value &= ~(GPIO_OUT_ENABLE_BIT_GPIO49); // 0=Output Enabled, 1=Tristate
+	pci_write_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL, value);
+
+	value  = pci_read_config8(sm_dev, PCI_REG_GPIO_48_47_46_37_CNTRL);
+	value &= ~(GPIO_OUT_BIT_GPIO48);
+	value |= (~(socket_id & 1)) << 3;  // Output of GPIO48 is inverse of SocketId
+	value &= ~(GPIO_OUT_ENABLE_BIT_GPIO48); // 0=Output Enabled, 1=Tristate
+	pci_write_config8(sm_dev, PCI_REG_GPIO_48_47_46_37_CNTRL, value);
+
+	return gpio52_to_49;
+}
+
+static void restore_socket(UINT8 original_value)
+{
+	device_t sm_dev = PCI_DEV(0, 0x14, 0); //SMBUS
+	pci_write_config8(sm_dev, PCI_REG_GPIO_52_to_49_CNTRL, original_value);
+
+	// TODO: Restore previous GPIO48 configurations?
+	//pci_write_config8(sm_dev, PCI_REG_GPIO_48_47_46_37_CNTRL, gpio48_47_46_37_save);
+}
+#endif
 
 STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
 {
@@ -81,8 +137,6 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] =
 	},
 };
 
-extern AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info);
-
 AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
 	UINTN i;
@@ -487,7 +541,20 @@ AGESA_STATUS BiosReset (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
 {
 	AGESA_STATUS Status;
-	Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
+#ifdef __PRE_RAM__
+	UINT8 original_value = 0;
+
+	if (ConfigPtr == NULL)
+		return AGESA_ERROR;
+
+	original_value = select_socket(((AGESA_READ_SPD_PARAMS *)ConfigPtr)->SocketId);
+
+	Status = agesa_ReadSPD (Func, Data, ConfigPtr);
+
+	restore_socket(original_value);
+#else
+	Status = AGESA_UNSUPPORTED;
+#endif
 
 	return Status;
 }