diff options
author | Kimarie Hoot <kimarie.hoot@se-eng.com> | 2013-03-08 15:31:49 -0700 |
---|---|---|
committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2013-03-20 05:54:12 +0100 |
commit | b37ec540affaaeb3a8a230895c08778c54f1d076 (patch) | |
tree | 44aa76c2f7e502781d4e5f051f4dbb04ff7f1349 /src/mainboard/tyan/s8226/devicetree.cb | |
parent | eef45f9cfd016343fbcf92b4df5b3d76a39c5136 (diff) | |
download | coreboot-b37ec540affaaeb3a8a230895c08778c54f1d076.tar.xz |
Tyan S8226: Use SPD read code from F15 wrapper
Changes:
- Get rid of the s8226 mainboard specific code and use the
platform generic function wrapper that was added in change
http://review.coreboot.org/#/c/2777/
AMD Fam15: Add SPD read functions to wrapper code
- Move DIMM addresses into devicetree.cb
Notes:
- The DIMM reads only happen in romstage, so the function is not
available in ramstage. Point the read-SPD callback to a generic
function in ramstage.
- select_socket() and restore_socket() started by duplicating
sp5100_set_gpio() and sp5100_restore_gpio(), which were in
dimmSpd.c. In addition to renaming the functions to more
specifically state their purpose, some cleanup and magic number
reduction was done.
Change-Id: I1eaf64986ef4fa3f89aed2b69d3f9c8c913f726f
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2827
Tested-by: build bot (Jenkins)
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/tyan/s8226/devicetree.cb')
-rw-r--r-- | src/mainboard/tyan/s8226/devicetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/tyan/s8226/devicetree.cb b/src/mainboard/tyan/s8226/devicetree.cb index 420e52fd0d..f879ec5308 100644 --- a/src/mainboard/tyan/s8226/devicetree.cb +++ b/src/mainboard/tyan/s8226/devicetree.cb @@ -121,6 +121,12 @@ chip northbridge/amd/agesa/family15/root_complex device pci 18.3 on end device pci 18.4 on end device pci 18.5 on end #f15 + + register "spdAddrLookup" = " + { + { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 0 + { {0xA0, 0xA4, 0xA8}, {0xA2, 0xA6, 0xAA}, }, // socket 1 + }" end #chip northbridge/amd/agesa/family15 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family15/root_complex |