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authorStefan Reinauer <stepan@coresystems.de>2010-04-14 18:59:42 +0000
committerStefan Reinauer <stepan@openbios.org>2010-04-14 18:59:42 +0000
commit523ebd927d80807fa8a8c30cddfe0f549b7f62d8 (patch)
treed26cc7520f89d16260fa1cd989512834bb7dc962 /src/mainboard/tyan
parent97b21be8c74a2e9da5a7c01944a727e0bab05170 (diff)
downloadcoreboot-523ebd927d80807fa8a8c30cddfe0f549b7f62d8.tar.xz
zero warning days. Move RAMTOP and RAMBASE together.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan')
-rw-r--r--src/mainboard/tyan/s2735/reset.c1
-rw-r--r--src/mainboard/tyan/s2735/romstage.c15
-rw-r--r--src/mainboard/tyan/s2912/romstage.c10
-rw-r--r--src/mainboard/tyan/s2912_fam10/romstage.c2
4 files changed, 5 insertions, 23 deletions
diff --git a/src/mainboard/tyan/s2735/reset.c b/src/mainboard/tyan/s2735/reset.c
index 2601faa676..d40d254cc5 100644
--- a/src/mainboard/tyan/s2735/reset.c
+++ b/src/mainboard/tyan/s2735/reset.c
@@ -1,3 +1,4 @@
+#include <reset.h>
void i82801ex_hard_reset(void);
/* FIXME: There's another hard_reset() in romstage.c. Why? */
diff --git a/src/mainboard/tyan/s2735/romstage.c b/src/mainboard/tyan/s2735/romstage.c
index 40a9863a22..0a74579b89 100644
--- a/src/mainboard/tyan/s2735/romstage.c
+++ b/src/mainboard/tyan/s2735/romstage.c
@@ -32,15 +32,6 @@ static void hard_reset(void)
outb(0x0e, 0x0cf9);
}
-static void soft_reset(void)
-{
-#if 1
- /* link reset */
- outb(0x02, 0x0cf9);
- outb(0x06, 0x0cf9);
-#endif
-}
-
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
@@ -61,14 +52,10 @@ void main(unsigned long bist)
},
};
- unsigned cpu_reset = 0;
-
if (bist == 0) {
enable_lapic();
}
-// post_code(0x32);
-
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -76,8 +63,6 @@ void main(unsigned long bist)
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
-// setup_s2735_resource_map();
-
if(bios_reset_detected()) {
hard_reset();
}
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index c525ab773c..3b79a29153 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -143,8 +143,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
-
- unsigned value;
uint32_t dword;
uint8_t byte;
@@ -160,21 +158,21 @@ static void sio_setup(void)
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-
}
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
+ // Node 0
(0xa<<3)|0, (0xa<<3)|2, 0, 0,
(0xa<<3)|1, (0xa<<3)|3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ // Node 1
(0xa<<3)|4, (0xa<<3)|6, 0, 0,
(0xa<<3)|5, (0xa<<3)|7, 0, 0,
-#endif
};
- struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
int needs_reset = 0;
unsigned bsp_apicid = 0;
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 2734c02785..128f3b3f49 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -126,7 +126,6 @@ static inline int spd_read_byte(unsigned device, unsigned address)
static void sio_setup(void)
{
- unsigned value;
uint32_t dword;
uint8_t byte;
@@ -142,7 +141,6 @@ static void sio_setup(void)
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-
}
#include "spd_addr.h"