summaryrefslogtreecommitdiff
path: root/src/mainboard/tyan
diff options
context:
space:
mode:
authorMartin Roth <martinroth@google.com>2017-06-24 21:54:33 -0600
committerMartin Roth <martinroth@google.com>2017-07-06 00:20:06 +0000
commit43927bae1846e0768cbfad717f4820f408cde82b (patch)
tree3752707f9ecc93f8d125682f6dfb89896ff5db15 /src/mainboard/tyan
parent356b519049e6d40e15b2e4a85cae654e2e8df8ba (diff)
downloadcoreboot-43927bae1846e0768cbfad717f4820f408cde82b.tar.xz
mainboard/[m-w]: add IS_ENABLED() around Kconfig symbol references
Change-Id: Ifba3257b0328d0b6ad1bee9bf885683998df5851 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/20344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/tyan')
-rw-r--r--src/mainboard/tyan/s2912/romstage.c4
-rw-r--r--src/mainboard/tyan/s2912_fam10/romstage.c4
-rw-r--r--src/mainboard/tyan/s8226/buildOpts.c4
-rw-r--r--src/mainboard/tyan/s8226/rd890_cfg.h4
-rw-r--r--src/mainboard/tyan/s8226/sb700_cfg.h8
5 files changed, 12 insertions, 12 deletions
diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c
index 6a47612dbe..89f3175c25 100644
--- a/src/mainboard/tyan/s2912/romstage.c
+++ b/src/mainboard/tyan/s2912/romstage.c
@@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
setup_coherent_ht_domain(); // routing table and start other core0
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS
+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
// It is said that we should start core1 after all core0 launched
/* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
* So here need to make sure last core0 is started, esp for two way system,
@@ -153,7 +153,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
/* it will set up chains and store link pair for optimization later */
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-#if CONFIG_SET_FIDVID
+#if IS_ENABLED(CONFIG_SET_FIDVID)
{
msr_t msr;
msr = rdmsr(0xc0010042);
diff --git a/src/mainboard/tyan/s2912_fam10/romstage.c b/src/mainboard/tyan/s2912_fam10/romstage.c
index 4c8c19f665..b449f77731 100644
--- a/src/mainboard/tyan/s2912_fam10/romstage.c
+++ b/src/mainboard/tyan/s2912_fam10/romstage.c
@@ -174,7 +174,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
*/
wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS
+#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores(bsp_apicid);
@@ -184,7 +184,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x38);
-#if CONFIG_SET_FIDVID
+#if IS_ENABLED(CONFIG_SET_FIDVID)
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c
index 13128920b9..e27ec163ee 100644
--- a/src/mainboard/tyan/s8226/buildOpts.c
+++ b/src/mainboard/tyan/s8226/buildOpts.c
@@ -426,10 +426,10 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
*/
/*
-#if CONFIG_CPU_AMD_AGESA_FAMILY15
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define BLDOPT_REMOVE_FAMILY_10_SUPPORT TRUE
#endif
-#if CONFIG_CPU_AMD_AGESA_FAMILY10
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define BLDOPT_REMOVE_FAMILY_15_SUPPORT TRUE
#endif
*/
diff --git a/src/mainboard/tyan/s8226/rd890_cfg.h b/src/mainboard/tyan/s8226/rd890_cfg.h
index 35ddfbb5b5..6607094281 100644
--- a/src/mainboard/tyan/s8226/rd890_cfg.h
+++ b/src/mainboard/tyan/s8226/rd890_cfg.h
@@ -27,10 +27,10 @@
* [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
*/
#ifndef DEFAULT_HT_PATH
-#if CONFIG_CPU_AMD_AGESA_FAMILY10
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10)
#define DEFAULT_HT_PATH {0x0, 0x3}
#endif
-#if CONFIG_CPU_AMD_AGESA_FAMILY15
+#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15)
#define DEFAULT_HT_PATH {0x0, 0x1}
#endif
#endif
diff --git a/src/mainboard/tyan/s8226/sb700_cfg.h b/src/mainboard/tyan/s8226/sb700_cfg.h
index 3f82931684..bed9161f29 100644
--- a/src/mainboard/tyan/s8226/sb700_cfg.h
+++ b/src/mainboard/tyan/s8226/sb700_cfg.h
@@ -36,13 +36,13 @@
* before AGESA module get call.
*/
#ifndef BIOS_SIZE
-#if CONFIG_COREBOOT_ROMSIZE_KB_1024
+#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024)
#define BIOS_SIZE BIOS_SIZE_1M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_2048
+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048)
#define BIOS_SIZE BIOS_SIZE_2M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_4096
+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096)
#define BIOS_SIZE BIOS_SIZE_4M
-#elif CONFIG_COREBOOT_ROMSIZE_KB_8192
+#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192)
#define BIOS_SIZE BIOS_SIZE_8M
#endif
#endif