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authorCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-04-03 02:18:23 +0000
committerCarl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>2009-04-03 02:18:23 +0000
commit73ad3264525c7d076ef2aafab63841685bf53679 (patch)
tree1ab5546586def7f180b4dbf0847f7968bb49be59 /src/mainboard/tyan
parente729846b64eed59e72080766d09036ebbe9760a7 (diff)
downloadcoreboot-73ad3264525c7d076ef2aafab63841685bf53679.tar.xz
There are more than a dozen targets in the v2 tree which refer to ROMCC
in their Config.lb but never use it. There's no point in keeping dead code around. Kill it. This patch removes ROMCC remainders from Config.lb for tyan/s2735 and tyan/s2850. Abuild build log with and without the patch is completely identical. More patches of the same type can be done, hopefully making ROMCC dependencies a bit more clear for v2. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/tyan')
-rw-r--r--src/mainboard/tyan/s2735/Config.lb56
-rw-r--r--src/mainboard/tyan/s2850/Config.lb58
2 files changed, 0 insertions, 114 deletions
diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb
index 8c90c1dfd3..14c2eff63f 100644
--- a/src/mainboard/tyan/s2735/Config.lb
+++ b/src/mainboard/tyan/s2735/Config.lb
@@ -35,7 +35,6 @@ default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
arch i386 end
-
##
## Build the objects we have code for in this directory.
##
@@ -44,8 +43,6 @@ driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
object reset.o
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./auto.o
@@ -63,31 +60,6 @@ makerule ./auto.inc
end
end
-else
-
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
##
## Build our 16 bit and 32 bit coreboot entry code
@@ -95,7 +67,6 @@ end
mainboardinit cpu/x86/16bit/entry16.inc
mainboardinit cpu/x86/32bit/entry32.inc
ldscript /cpu/x86/16bit/entry16.lds
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -103,7 +74,6 @@ if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/car/cache_as_ram.lds
end
-end
##
@@ -117,24 +87,16 @@ else
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/x86/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -142,36 +104,18 @@ end
### failover to another image.
###
if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
- ldscript /arch/i386/lib/failover.lds
-else
ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
end
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
-# ROMCC
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
##
## Include the secondary Configuration files
##
diff --git a/src/mainboard/tyan/s2850/Config.lb b/src/mainboard/tyan/s2850/Config.lb
index 2a3bffe642..3dd950b255 100644
--- a/src/mainboard/tyan/s2850/Config.lb
+++ b/src/mainboard/tyan/s2850/Config.lb
@@ -45,8 +45,6 @@ driver mainboard.o
if HAVE_MP_TABLE object mptable.o end
if HAVE_PIRQ_TABLE object irq_tables.o end
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
makerule ./auto.o
@@ -64,31 +62,6 @@ makerule ./auto.inc
end
end
-else
-
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ../romcc"
- action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ../romcc"
- action "../romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-end
##
## Build our 16 bit and 32 bit coreboot entry code
##
@@ -99,7 +72,6 @@ end
mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/x86/32bit/entry32.lds
end
@@ -107,7 +79,6 @@ if USE_DCACHE_RAM
if CONFIG_USE_INIT
ldscript /cpu/amd/car/cache_as_ram.lds
end
-end
##
## Build our reset vector (This is where coreboot is entered)
@@ -120,24 +91,16 @@ else
ldscript /cpu/x86/32bit/reset32.lds
end
-if USE_DCACHE_RAM
-else
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-end
-
##
## Include an id string (For safe flashing)
##
mainboardinit arch/i386/lib/id.inc
ldscript /arch/i386/lib/id.lds
-if USE_DCACHE_RAM
##
## Setup Cache-As-Ram
##
mainboardinit cpu/amd/car/cache_as_ram.inc
-end
###
### This is the early phase of coreboot startup
@@ -145,12 +108,7 @@ end
### failover to another image.
###
if USE_FALLBACK_IMAGE
-if USE_DCACHE_RAM
- ldscript /arch/i386/lib/failover.lds
-else
ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
end
###
@@ -160,28 +118,12 @@ end
##
## Setup RAM
##
-if USE_DCACHE_RAM
-
if CONFIG_USE_INIT
initobject auto.o
else
mainboardinit ./auto.inc
end
-else
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-end
-
##
## Include the secondary Configuration files
##