s2735 half update

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

8 files changed, 212 insertions, 247 deletions

diff --git a/src/mainboard/tyan/s2735/Config.lb b/src/mainboard/tyan/s2735/Config.lb
index a5de70ba1b..eb1bb5c934 100644
--- a/src/mainboard/tyan/s2735/Config.lb
+++ b/src/mainboard/tyan/s2735/Config.lb
@@ -1,230 +1,200 @@
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses ARCH
-uses HARD_RESET_BUS
-uses HARD_RESET_DEVICE
-uses HARD_RESET_FUNCTION
-#
-#
-###
-### Set all of the defaults for an x86 architecture
-###
-#
-#
-###
-### Build the objects we have code for in this directory.
-###
-##object mainboard.o
-config chip.h
-register "fixup_scsi" = "1" 
-register "fixup_vga" = "1"
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+	default ROM_SECTION_SIZE   = FALLBACK_SIZE
+	default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+	default ROM_SECTION_SIZE   = ( ROM_SIZE - FALLBACK_SIZE )
+	default ROM_SECTION_OFFSET = 0
+end
 
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE            = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE      = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+arch i386 end 
 
 ##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
+## Build the objects we have code for in this directory.
 ##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
 
 driver mainboard.o
-#dir /drvers/adaptec/7902
-#dir /drivers/si/3114
-#dir /drivers/intel/82551_ipmi
-#dir /drivers/ati/ragexl
 if HAVE_MP_TABLE object mptable.o end
 if HAVE_PIRQ_TABLE object irq_tables.o end
-#
-#default HARD_RESET_BUS=1
-#default HARD_RESET_DEVICE=4
-#default HARD_RESET_FUNCTION=0
-#
-arch i386 end
-#
-###
-### Build our 16 bit and 32 bit linuxBIOS entry code
-###
-mainboardinit cpu/i386/entry16.inc
-mainboardinit cpu/i386/entry32.inc
-mainboardinit cpu/i386/bist32.inc
-ldscript /cpu/i386/entry16.lds
-ldscript /cpu/i386/entry32.lds
-#
-###
-### Build our reset vector (This is where linuxBIOS is entered)
-###
-if USE_FALLBACK_IMAGE 
-	mainboardinit cpu/i386/reset16.inc 
-	ldscript /cpu/i386/reset16.lds 
-else
-	mainboardinit cpu/i386/reset32.inc 
-	ldscript /cpu/i386/reset32.lds 
-end
-#
-#### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-#
-###
-### Include an id string (For safe flashing)
-###
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-#
-####
-#### This is the early phase of linuxBIOS startup 
-#### Things are delicate and we test to see if we should
-#### failover to another image.
-####
-#option MAX_REBOOT_CNT=2
-if USE_FALLBACK_IMAGE
-  ldscript /arch/i386/lib/failover.lds 
-end
-#
-###
-### Setup our mtrrs
-###
-#mainboardinit cpu/p6/earlymtrr.inc
-###
-### Only the bootstrap cpu makes it here.
-### Failover if we need to 
-###
-#
-if USE_FALLBACK_IMAGE
-  mainboardinit ./failover.inc
-end
-
-#
-#
-###
-### Setup the serial port
-###
-mainboardinit pc80/serial.inc
-mainboardinit arch/i386/lib/console.inc
-mainboardinit cpu/i386/bist32_fail.inc
-#
-####
-#### O.k. We aren't just an intermediary anymore!
-####
-#
-###
-### When debugging disable the watchdog timer
-###
-##option MAXIMUM_CONSOLE_LOGLEVEL=7
-#default MAXIMUM_CONSOLE_LOGLEVEL=7
-#
-#if USE_FALLBACK_IMAGE mainboardinit arch/i386/lib/noop_failover.inc  end
-#
-###
-### Romcc output
-###
+#object reset.o
 
+##
+## Romcc output
+##
 makerule ./failover.E
 	depends "$(MAINBOARD)/failover.c" 
 	action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
 end
 
 makerule ./failover.inc
-	depends "./romcc ./failover.E"
+	depends "./failover.E ./romcc"
 	action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
 end
 
 makerule ./auto.E 
-        depends "$(MAINBOARD)/auto.c option_table.h"
-        action  "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
+	depends	"$(MAINBOARD)/auto.c option_table.h " 
+	action	"$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
 end
 makerule ./auto.inc 
-	depends "./romcc ./auto.E"
-	action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E" 
-#        action  "./romcc -O2 ./auto.E > auto.inc"
+	depends "./auto.E ./romcc"
+	action	"./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
 end
-mainboardinit cpu/p6/enable_mmx_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/p6/disable_mmx_sse.inc
-#
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE 
+	mainboardinit cpu/x86/16bit/reset16.inc 
+	ldscript /cpu/x86/16bit/reset16.lds 
+else
+	mainboardinit cpu/x86/32bit/reset32.inc 
+	ldscript /cpu/x86/32bit/reset32.lds 
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup 
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+	ldscript /arch/i386/lib/failover.lds 
+	mainboardinit ./failover.inc
+end
+
 ###
-### Include the secondary Configuration files 
+### O.k. We aren't just an intermediary anymore!
 ###
 
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files 
+##
+dir /pc80
 config chip.h
 
+# sample config for tyan/s2735
 chip northbridge/intel/e7501
-	device pci_domain 0
-		device pci 0.0 on end 
-		device pci 0.1 on end
-		device pci 2.0 on 
-			chip southbridge/intel/i82870
-				device pci 1c.0
-				device pci 1d.0
-				device pci 1e.0
-				device pci 1f.0
-			end
-		end
-		device pci 6.0 on end
-		chip southbridge/intel/i82801er
-			device pci 1d.0 on end
-			device pci 1d.1 on end
-			device pci 1d.2 on end
-			device pci 1d.3 on end
-			device pci 1d.7 on end
-			device pci 1e.0 on end
-			device pci 1f.0 on 
-				# device pci 8.0 end
-				chip winbond/w83627hf
-		                        device pnp 2e.0 on     #  Floppy
-		                                 io 0x60 = 0x3f0
-		                                irq 0x70 = 6
-		                                drq 0x74 = 2
-					end
-		                        device pnp 2e.1 off     #  Parallel Port
-		                                 io 0x60 = 0x378
-		                                irq 0x70 = 7
-					end
-		                        device pnp 2e.2 on      #  Com1
-		                                 io 0x60 = 0x3f8
-		                                irq 0x70 = 4
-					end
-		                        device pnp 2e.3 off     #  Com2
-		                                 io 0x60 = 0x2f8
-		                                irq 0x70 = 3
-					end
-		                        device pnp 2e.5 on      #  Keyboard
-		                                 io 0x60 = 0x60
-		                                 io 0x62 = 0x64
-		                                irq 0x70 = 1
-						irq 0x72 = 12
-					end
-		                        device pnp 2e.6 off end #  CIR
-		                        device pnp 2e.7 off end #  GAME_MIDI_GIPO1
-		                        device pnp 2e.8 off end #  GPIO2
-		                        device pnp 2e.9 off end #  GPIO3
-		                        device pnp 2e.a off end #  ACPI
-		                        device pnp 2e.b on      #  HW Monitor
-						 io 0x60 = 0x290
-					end
-				end
-			end
-			device pci 1f.1 off end
-			device pci 1f.2 on end
-			device pci 1f.3 on end
-			device pci 1f.5 off end
-			device pci 1f.6 off end
-		
-		end
-	end
-	device apic_cluster 0
-		chip cpu/intel/socket_mPGA604_533Mhz
-			apic 0
-		end
-		chip cpu/intel/socket_mPGA604_533Mhz
-			apic 6
-		end
-	end
+        device pci_domain 0 on
+                device pci 0.0 on end
+                device pci 0.1 on end
+                device pci 2.0 on
+                        chip southbridge/intel/i82870
+                                device pci 1c.0 on end
+                                device pci 1d.0 on end
+                                device pci 1e.0 on end
+                                device pci 1f.0 on end
+                        end
+                end
+                device pci 6.0 on end
+                chip southbridge/intel/i82801er
+                        device pci 1d.0 on end
+                        device pci 1d.1 on end
+                        device pci 1d.2 on end
+                        device pci 1d.3 on end
+                        device pci 1d.7 on end
+                        device pci 1e.0 on end
+                        device pci 1f.0 on
+                                # device pci 8.0 end
+                                chip superio/winbond/w83627hf
+                                        device pnp 2e.0 on     #  Floppy
+                                                 io 0x60 = 0x3f0
+                                                irq 0x70 = 6
+                                                drq 0x74 = 2
+                                        end
+                                        device pnp 2e.1 off     #  Parallel Port
+                                                 io 0x60 = 0x378
+                                                irq 0x70 = 7
+                                        end
+                                        device pnp 2e.2 on      #  Com1
+                                                 io 0x60 = 0x3f8
+                                                irq 0x70 = 4
+                                        end
+                                        device pnp 2e.3 off     #  Com2
+                                                 io 0x60 = 0x2f8
+                                                irq 0x70 = 3
+                                        end
+                                        device pnp 2e.5 on      #  Keyboard
+                                                 io 0x60 = 0x60
+                                                 io 0x62 = 0x64
+                                                irq 0x70 = 1
+                                                irq 0x72 = 12
+                                        end
+                                        device pnp 2e.6 off end #  CIR
+                                        device pnp 2e.7 off end #  GAME_MIDI_GIPO1
+                                        device pnp 2e.8 off end #  GPIO2
+                                        device pnp 2e.9 off end #  GPIO3
+                                        device pnp 2e.a off end #  ACPI
+                                        device pnp 2e.b on      #  HW Monitor
+                                                 io 0x60 = 0x290
+                                        end
+                                end
+                        end
+                        device pci 1f.1 off end
+                        device pci 1f.2 on end
+                        device pci 1f.3 on end
+                        device pci 1f.5 off end
+                        device pci 1f.6 off end
+
+                end
+        end
+        device apic_cluster 0 on
+                chip cpu/intel/socket_mPGA604_533Mhz
+                        device apic 0 on end
+                end
+                chip cpu/intel/socket_mPGA604_533Mhz
+                        device apic 6 on end
+                end
+        end
 end
 
-dir /pc80
-#dir /bioscall
diff --git a/src/mainboard/tyan/s2735/auto.c b/src/mainboard/tyan/s2735/auto.c
index 3a99aa29a9..c2e59285fb 100644
--- a/src/mainboard/tyan/s2735/auto.c
+++ b/src/mainboard/tyan/s2735/auto.c
@@ -1,10 +1,12 @@
 #define ASSEMBLY 1
+
 #include <stdint.h>
 #include <device/pci_def.h>
 #include <arch/io.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
 #include "pc80/serial.c"
@@ -12,17 +14,13 @@
 #include "ram/ramtest.c"
 #include "southbridge/intel/i82801er/i82801er_early_smbus.c"
 #include "northbridge/intel/e7501/raminit.h"
-
-#if 1
-#include "cpu/p6/apic_timer.c"
+#include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-#endif
-
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/intel/e7501/debug.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c" 
-
-#include "cpu/p6/earlymtrr.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "cpu/x86/bist.h"
 
 #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
 
@@ -55,7 +53,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "northbridge/intel/e7501/reset_test.c"
 #include "sdram/generic_sdram.c"
 
-static void main(void)
+static void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {
 		{
@@ -66,14 +64,21 @@ static void main(void)
 		},
 	};
 
-#if 1
-        enable_lapic();
-        init_timer();
-#endif
-        
+        if (bist == 0) {
+                /* Skip this if there was a built in self test failure */
+                early_mtrr_init();
+                enable_lapic();
+                init_timer();
+
+        }
+
         w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
         uart_init();
         console_init();
+
+        /* Halt if there was a built in self test failure */
+	report_bist_failure(bist);
+
 //        setup_default_resource_map();
 #if 0
 	print_pci_devices();
diff --git a/src/mainboard/tyan/s2735/chip.h b/src/mainboard/tyan/s2735/chip.h
index bdde8a6df5..d63c156af5 100644
--- a/src/mainboard/tyan/s2735/chip.h
+++ b/src/mainboard/tyan/s2735/chip.h
@@ -1,4 +1,4 @@
-extern struct chip_operations mainboard_tyan_s2735_control;
+extern struct chip_operations mainboard_tyan_s2735_ops;
 
 struct mainboard_tyan_s2735_config {
 	int fixup_scsi;
diff --git a/src/mainboard/tyan/s2735/failover.c b/src/mainboard/tyan/s2735/failover.c
index 6ba3cae62a..91cd69317c 100644
--- a/src/mainboard/tyan/s2735/failover.c
+++ b/src/mainboard/tyan/s2735/failover.c
@@ -4,22 +4,14 @@
 #include <device/pci_ids.h>
 #include <arch/io.h>
 #include <arch/romcc_io.h>
-#include <arch/smp/lapic.h>
+#include <cpu/x86/lapic.h>
 #include "pc80/mc146818rtc_early.c"
 #include "southbridge/intel/i82801er/cmos_failover.c"
-#include "cpu/p6/boot_cpu.c"
+#include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/intel/e7501/reset_test.c"
 
-#define HAVE_REGPARM_SUPPORT 0
-#if HAVE_REGPARM_SUPPORT
 static unsigned long main(unsigned long bist)
 {
-#else
-static void main(void)
-{
-	unsigned long bist = 0;
-	
-#endif
 	/* Is this a deliberate reset by the bios */
 	if (bios_reset_detected() && last_boot_normal()) {
 		goto normal_image;
@@ -51,9 +43,5 @@ static void main(void)
 		);
 #endif
  fallback_image:
-#if HAVE_REGPARM_SUPPORT
 	return bist;
-#else
-	return;
-#endif
 }
diff --git a/src/mainboard/tyan/s2735/mainboard.c b/src/mainboard/tyan/s2735/mainboard.c
index 2531a701d9..ccc3a93b27 100644
--- a/src/mainboard/tyan/s2735/mainboard.c
+++ b/src/mainboard/tyan/s2735/mainboard.c
@@ -139,10 +139,10 @@ static struct device_operations mainboard_operations = {
 
 static void enable_dev(device_t dev)
 {
-	dev->ops = &mainboard_ops;
+	dev->ops = &mainboard_operations;
 }
 
-struct chip_operations mainboard_tyan_s2735_control = {
+struct chip_operations mainboard_tyan_s2735_ops = {
         .enable_dev = enable_dev,
         .name      = "Tyan s2735 mainboard ",
 };
diff --git a/src/mainboard/tyan/s2735/mptable.c b/src/mainboard/tyan/s2735/mptable.c
index 25b1929eba..35baeb31ce 100644
--- a/src/mainboard/tyan/s2735/mptable.c
+++ b/src/mainboard/tyan/s2735/mptable.c
@@ -4,7 +4,7 @@
 #include <string.h>
 #include <stdint.h>
 
-void *smp_write_config_table(void *v, unsigned long * processor_map)
+void *smp_write_config_table(void *v)
 {
         static const char sig[4] = "PCMP";
         static const char oem[8] = "TYAN    ";
@@ -28,7 +28,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
         mc->mpe_checksum = 0;
         mc->reserved = 0;
 
-        smp_write_processors(mc, processor_map);
+        smp_write_processors(mc);
 
 
 /*Bus:		Bus ID	Type*/
@@ -41,19 +41,21 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
 /*I/O APICs:	APIC ID	Version	State		Address*/
 	smp_write_ioapic(mc, 8, 0x20, 0xfec00000);
 	{
-		struct pci_dev *dev;
-		uint32_t base;
+                device_t dev;
+                struct resource *res;
 		dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
 		if (dev) {
-			base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-			base &= PCI_BASE_ADDRESS_MEM_MASK;
-			smp_write_ioapic(mc, 9, 0x20, base);
+                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
+                        if (res) {
+                                smp_write_ioapic(mc, 0x09, 0x20, res->base);
+                        }		
 		}
 		dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
 		if (dev) {
-			base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
-			base &= PCI_BASE_ADDRESS_MEM_MASK;
-			smp_write_ioapic(mc, 0xa, 0x20, base);
+                        res = find_resource(dev, PCI_BASE_ADDRESS_0);
+                        if (res) {
+                                smp_write_ioapic(mc, 0x0a, 0x20, res->base);
+                        }		
 		}
 	}
 /*I/O Ints:	Type	Polarity    Trigger	Bus ID	 IRQ	APIC ID	PIN#
@@ -157,9 +159,9 @@ Compatibility Bus Address
 	return smp_next_mpe_entry(mc);
 }
 
-unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
+unsigned long write_smp_table(unsigned long addr)
 {
 	void *v;
 	v = smp_write_floating_table(addr);
-	return (unsigned long)smp_write_config_table(v, processor_map);
+	return (unsigned long)smp_write_config_table(v);
 }
diff --git a/src/mainboard/tyan/s4880/Options.lb b/src/mainboard/tyan/s4880/Options.lb
index 6aa9778a12..da285a5f6a 100644
--- a/src/mainboard/tyan/s4880/Options.lb
+++ b/src/mainboard/tyan/s4880/Options.lb
@@ -105,7 +105,7 @@ default LB_CKS_LOC=123
 ## Only worry about 2 micro processors
 ##
 default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
+default CONFIG_MAX_CPUS=4
 
 ##
 ## Build code to setup a generic IOAPIC
diff --git a/src/mainboard/tyan/s4882/Options.lb b/src/mainboard/tyan/s4882/Options.lb
index 0462ee4ec7..948f71ea85 100644
--- a/src/mainboard/tyan/s4882/Options.lb
+++ b/src/mainboard/tyan/s4882/Options.lb
@@ -105,7 +105,7 @@ default LB_CKS_LOC=123
 ## Only worry about 2 micro processors
 ##
 default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
+default CONFIG_MAX_CPUS=4
 
 ##
 ## Build code to setup a generic IOAPIC