zero warnings days.

The tyan s2895 is down to 3 warnings, 2 of which are caused by #warning.

The 1000 ways of how the AMD code waits for the cores to be started up 
are a real pain for the brain.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 8 insertions, 25 deletions

diff --git a/src/mainboard/tyan/s2895/romstage.c b/src/mainboard/tyan/s2895/romstage.c
index 8a5f80bc92..e62c2a5c05 100644
--- a/src/mainboard/tyan/s2895/romstage.c
+++ b/src/mainboard/tyan/s2895/romstage.c
@@ -15,35 +15,26 @@
 #include <cpu/x86/lapic.h>
 #include "option_table.h"
 #include "pc80/mc146818rtc_early.c"
-
 #include "pc80/serial.c"
 #include "console/console.c"
 #include "lib/ramtest.c"
-
 #include <cpu/amd/model_fxx_rev.h>
-
 #include "northbridge/amd/amdk8/incoherent_ht.c"
 #include "southbridge/nvidia/ck804/ck804_early_smbus.c"
 #include "northbridge/amd/amdk8/raminit.h"
 #include "cpu/amd/model_fxx/apic_timer.c"
 #include "lib/delay.c"
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdk8/reset_test.c"
 #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
 #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
 #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
 #define SUPERIO_GPIO_IO_BASE 0x400
-
 #include "cpu/x86/bist.h"
-
 #include "northbridge/amd/amdk8/debug.c"
-
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-
+#include <cpu/amd/mtrr.h>
+#include "cpu/x86/mtrr/earlymtrr.c"
 #include "northbridge/amd/amdk8/setup_resource_map.c"
-
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
 
 static void memreset_setup(void)
@@ -54,15 +45,14 @@ static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
 
-static void sio_gpio_setup(void){
-
+static void sio_gpio_setup(void)
+{
 	unsigned value;
 
 	/*Enable onboard scsi*/
 	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
 	value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
 	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
-
 }
 
 static inline void activate_spd_rom(const struct mem_controller *ctrl)
@@ -111,10 +101,9 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 static void sio_setup(void)
 {
-
 	unsigned value;
-	uint32_t dword;
-	uint8_t byte;
+	u32 dword;
+	u8 byte;
 
 	pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400);
 
@@ -134,18 +123,15 @@ static void sio_setup(void)
 	value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77);
 	value &= 0xbf;
 	lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value);
-
 }
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-	static const uint16_t spd_addr [] = {
+	static const u16 spd_addr [] = {
 		(0xa<<3)|0, (0xa<<3)|2, 0, 0,
 		(0xa<<3)|1, (0xa<<3)|3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
 		(0xa<<3)|4, (0xa<<3)|6, 0, 0,
 		(0xa<<3)|5, (0xa<<3)|7, 0, 0,
-#endif
 	};
 
 	int needs_reset;
@@ -170,8 +156,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 		bsp_apicid = init_cpus(cpu_init_detectedx);
 	}
 
-//	post_code(0x32);
-
 	lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
 	uart_init();
 	console_init();
@@ -186,11 +170,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 	needs_reset = setup_coherent_ht_domain();
 
 	wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
+
 	// It is said that we should start core1 after all core0 launched
 	start_other_cores();
 	wait_all_other_cores_started(bsp_apicid);
-#endif
 
 	needs_reset |= ht_setup_chains_x();