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| author | Stefan Reinauer <reinauer@chromium.org> | 2015-07-29 23:54:38 -0700 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2015-10-30 18:24:39 +0100 |
| commit | 5fa4cb6d32b469ef8312de0c12ec648c085b9a1f (patch) | |
| tree | 7d25078fb59f9861880a4aaf1d9f807531e36637 /src/mainboard/tyan | |
| parent | d91ddc8d3181b8ab23726c8e744093f39473c202 (diff) | |
| download | coreboot-5fa4cb6d32b469ef8312de0c12ec648c085b9a1f.tar.xz | |
cpu/amd: Fix cbtypes.h to match UINTN convention
There are some inconsistencies in AMDs APIs between the coreboot
code and the vendorcode code. Unify the API.
UINTN maps to uintptr_t in UEFI land. Do the same
here. Also switch the other UEFI types to map to
fixed size types.
Change-Id: Ib46893c7cd5368eae43e9cda30eed7398867ac5b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/10601
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Diffstat (limited to 'src/mainboard/tyan')
| -rw-r--r-- | src/mainboard/tyan/s8226/rd890_cfg.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/tyan/s8226/rd890_cfg.c b/src/mainboard/tyan/s8226/rd890_cfg.c index 147d32bc31..a337714c62 100644 --- a/src/mainboard/tyan/s8226/rd890_cfg.c +++ b/src/mainboard/tyan/s8226/rd890_cfg.c @@ -226,7 +226,7 @@ void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CON pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS; pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS; - pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry; + pConfig->StandardHeader.CalloutPtr = (CALLOUT_ENTRY)&rd890_callout_entry; /* * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform. |