Various 440BX and Tyan S1846 related minor changes and fixes (trivial):

 - Only check the RAM from 0 - 640 KB and 768 KB - 1 MB now. That's
   available on all boards, regardless of what DIMMs you use.
   Tested on the Tyan S1846, works fine.

 - Properly set the PAM registers to allow the region from 768 KB - 1 MB
   to be used as normal RAM (required for the above).

 - Document all of this properly. Add/improve other documentation, too.

 - Simplify and document code in northbridge.c.

 - Cosmetics and coding style.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 14 insertions, 17 deletions

diff --git a/src/mainboard/tyan/s1846/Options.lb b/src/mainboard/tyan/s1846/Options.lb
index 896a49d940..1ce855231e 100644
--- a/src/mainboard/tyan/s1846/Options.lb
+++ b/src/mainboard/tyan/s1846/Options.lb
@@ -60,7 +60,6 @@ default HAVE_HARD_RESET=0
 ##
 default HAVE_PIRQ_TABLE=0
 default IRQ_SLOT_COUNT=4
-#object irq_tables.o
 
 ##
 ## Build code to export a CMOS option table
diff --git a/src/mainboard/tyan/s1846/auto.c b/src/mainboard/tyan/s1846/auto.c
index c4871d7710..7bb2a41788 100644
--- a/src/mainboard/tyan/s1846/auto.c
+++ b/src/mainboard/tyan/s1846/auto.c
@@ -31,7 +31,7 @@
 #include "ram/ramtest.c"
 #include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
 #include "northbridge/intel/i440bx/raminit.h"
-#include "mainboard/bitworks/ims/debug.c"  // FIXME
+#include "mainboard/bitworks/ims/debug.c"	// FIXME
 #include "pc80/udelay_io.c"
 #include "lib/delay.c"
 #include "superio/nsc/pc87309/pc87309_early_serial.c"
@@ -51,9 +51,7 @@ static inline int spd_read_byte(unsigned int device, unsigned int address)
 
 static void enable_mainboard_devices(void)
 {
-	device_t dev;
-
-	dev = pci_locate_device(PCI_ID(0x8086, 0x7110), 0);
+	device_t dev = pci_locate_device(PCI_ID(0x8086, 0x7110), 0);
 
 	if (dev == PCI_DEV_INVALID) {
 		die("Southbridge not found!\n");
@@ -66,13 +64,8 @@ static void main(unsigned long bist)
 {
 	static const struct mem_controller memctrl[] = {
 		{
-		 .d0 = PCI_DEV(0, 0, 0),
-		 .channel0 = {
-			      (0xa << 3) | 0,
-			      (0xa << 3) | 1,
-			      (0xa << 3) | 2,
-			      (0xa << 3) | 3,
-			      },
+			.d0 = PCI_DEV(0, 0, 0),
+			.channel0 = {0x50, 0x51, 0x52, 0x53},
 		 },
 	};
 
@@ -98,17 +91,22 @@ static void main(unsigned long bist)
 
 	/* Check whether RAM is working.
 	 *
-	 * Do _not_ check the area from 640 KB - 1 MB, as that's not really
-	 * RAM, but rather reserved for various other things:
+	 * Do _not_ check the area from 640 KB - 768 KB, as that's not really
+	 * RAM, but rather reserved for the 'Video Buffer Area'.
+	 *
+	 * Other stuff in the range from 640 KB - 1 MB:
 	 *
 	 *  - 640 KB - 768 KB: Video Buffer Area
 	 *  - 768 KB - 896 KB: Expansion Area
 	 *  - 896 KB - 960 KB: Extended System BIOS Area
 	 *  - 960 KB - 1 MB:   Memory (BIOS Area) - System BIOS Area
 	 *
-	 * Trying to check these areas will fail.
+	 * Trying to check these areas will usually fail, too. However, you
+	 * probably can set the PAM registers of the northbridge to map
+	 * those areas to RAM (read/write). In that case you can use the
+	 * range from 768 KB - 1 MB as normal RAM, and thus check it here.
 	 */
-	/* TODO: This is currently hardcoded to check 64 MB. */
 	ram_check(0x00000000, 0x0009ffff);	/* 0 - 640 KB */
-	ram_check(0x00100000, 0x007c0000);	/* 1 MB - 64 MB */
+	ram_check(0x000c0000, 0x00100000);	/* 768 KB - 1 MB */
+	// ram_check(0x00100000, 0x007c0000);   /* 1 MB - 64 MB */
 }