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| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-09-09 14:50:34 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-09-15 01:19:50 +0200 |
| commit | 563de15b8a4aafad162352754975158222f8de6c (patch) | |
| tree | e5af5a14a12cdd1f3153a259bc49bbd948274ce9 /src/mainboard/via/epia-cn | |
| parent | 16e9d459a09ae5833776e29926207d43d2fc9a02 (diff) | |
| download | coreboot-563de15b8a4aafad162352754975158222f8de6c.tar.xz | |
intel/amenia: Remove setting of GPIO_TIER1_SCI enable bit
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Diffstat (limited to 'src/mainboard/via/epia-cn')
0 files changed, 0 insertions, 0 deletions