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| author | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-10-01 14:50:12 +0000 |
|---|---|---|
| committer | Patrick Georgi <patrick.georgi@coresystems.de> | 2010-10-01 14:50:12 +0000 |
| commit | e82618d03719e1c3f012b6ac227aa4b34ae4950b (patch) | |
| tree | 8b346ea13157962dc040299579101958b9fe738f /src/mainboard/via/epia-m700 | |
| parent | f11b81d18d36ecf732452a861d79ecd75f380adc (diff) | |
| download | coreboot-e82618d03719e1c3f012b6ac227aa4b34ae4950b.tar.xz | |
Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,
rename it slightly, make it visible only on relevant northbridges,
drop it entirely from via boards (as they seem to have picked it
up from AMD code without using it themselves), and make it
default to false for all boards.
Some romstages used to set this to "true" (ie. "print debug output"),
but I didn't follow up on it in Kconfig - if you need it to debug CAR,
enable it yourself.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/via/epia-m700')
| -rw-r--r-- | src/mainboard/via/epia-m700/romstage.c | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/mainboard/via/epia-m700/romstage.c b/src/mainboard/via/epia-m700/romstage.c index abf87a77fc..479305fa2e 100644 --- a/src/mainboard/via/epia-m700/romstage.c +++ b/src/mainboard/via/epia-m700/romstage.c @@ -23,7 +23,6 @@ */ #define RAMINIT_SYSINFO 1 -#define CACHE_AS_RAM_ADDRESS_DEBUG 0 #define PAYLOAD_IS_SEABIOS 0 #include <stdint.h> |