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| author | Shaunak Saha <shaunak.saha@intel.com> | 2016-05-25 11:34:43 -0700 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-06-01 22:26:21 +0200 |
| commit | d6463dd42c0b5688601ce6de5e7cff16926df297 (patch) | |
| tree | 82e5f91bac541bffed52255f38c9d9ca0fca5857 /src/mainboard/via/epia-m850 | |
| parent | 7043bf353af14b5a11f18875e6e41ceac56ebfa7 (diff) | |
| download | coreboot-d6463dd42c0b5688601ce6de5e7cff16926df297.tar.xz | |
intel/apollolake: Add support to enable google ChromeEC
ChromeEC is needed for EC controlled features to work properly.
This patch adds neccessary support in soc/intel so that mainboard
asl files can include the ChromeEC e.g. PNOT method and
LPCB and also the nvs fields.
BUG = 53096
TEST = This patch is needed by the mainboard specific ASL change to include
src/ec/google/chromeec/acpi/ec.asl
Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/14967
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/mainboard/via/epia-m850')
0 files changed, 0 insertions, 0 deletions