diff options
author | Jon Harrison <bothlyn@blueyonder.co.uk> | 2009-07-01 10:57:25 +0000 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2009-07-01 10:57:25 +0000 |
commit | cfb9cd2f8ab545296f94cbc0580d0a9ae73efc06 (patch) | |
tree | 42646b998067600f07518b5dde4a8222aaf32127 /src/mainboard/via/epia-n/auto.c | |
parent | db8b4114ff73cc002bb4e15fd9e8f2fc012cf39e (diff) | |
download | coreboot-cfb9cd2f8ab545296f94cbc0580d0a9ae73efc06.tar.xz |
Ron,
Attached is the third revision of the CN400/EPIA-N(L) patch for CB V2.
Patch should work against r4381 (or later ?)
This version now boots all of the way through to attempting to launch a
payload (I'm trying FILO right now), where it falls over with exception
6 (invalid opcode)
The coreboot_table issue seems to have been automagically resolved by
the latest core files.
It may still be that the reason for the payload not starting is down to
some issue with the tables initialising, I'll look closer at that.
Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/via/epia-n/auto.c')
-rw-r--r-- | src/mainboard/via/epia-n/auto.c | 166 |
1 files changed, 166 insertions, 0 deletions
diff --git a/src/mainboard/via/epia-n/auto.c b/src/mainboard/via/epia-n/auto.c new file mode 100644 index 0000000000..031400e160 --- /dev/null +++ b/src/mainboard/via/epia-n/auto.c @@ -0,0 +1,166 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 VIA Technologies, Inc. + * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 + +#include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/via/cn400/raminit.h" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/lapic/boot_cpu.c" +#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "superio/winbond/w83697hf/w83697hf_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) + +/* + * NOOB :: + * d0f0 - Device 0 Function 0 etc. + */ +static const struct mem_controller ctrl = { + .d0f0 = 0x0000, + .d0f2 = 0x2000, + .d0f3 = 0x3000, + .d0f4 = 0x4000, + .d0f7 = 0x7000, + .d1f0 = 0x8000, + .channel0 = { 0x50 }, +}; + + +static void memreset_setup(void) +{ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/via/cn400/raminit.c" + +static void enable_mainboard_devices(void) +{ + device_t dev; + u8 reg; + + dev = pci_locate_device(PCI_ID(0x1106, 0x7259), 0); + if (dev == PCI_DEV_INVALID) + die("Northbridge V-Link not found!!!\n"); + pci_write_config8(dev, 0x4F, 0x01); + pci_write_config8(dev, 0x48, 0x13); + + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + if (dev == PCI_DEV_INVALID) + die("Southbridge not found!!!\n"); + + /* bit=0 means enable function (per VT8237R datasheet) + * 7 17.6 MC97 + * 6 17.5 AC97 + * 5 16.1 USB 2 + * 4 16.0 USB 1 + * 3 15.0 SATA and PATA + * 2 16.2 USB 3 + * 1 16.4 USB EHCI + */ + pci_write_config8(dev, 0x50, 0x80); + + /*bit=0 means enable internal function (per VT8237R datasheet) + * 7 USB Device Mode + *bit=1 means enable internal function (per VT8237R datasheet) + * 6 Reserved + * 5 LAN Controller Clock Gating + * 4 LAN Controller + * 3 Internal RTC + * 2 Internal PS2 Mouse + * 1 Internal KBC Configuration + * 0 Internal Keyboard Controller + */ + pci_write_config8(dev, 0x51, 0x1d); +} + +static void enable_shadow_ram(void) +{ + unsigned char shadowreg; + + shadowreg = pci_read_config8(ctrl.d0f3, 0x82); + /* 0xf0000-0xfffff Read/Write*/ + shadowreg |= 0x30; + pci_write_config8(ctrl.d0f3, 0x82, shadowreg); +} + +static void main(unsigned long bist) +{ + unsigned long x; + device_t dev; + + /* Enable multifunction for northbridge. */ + pci_write_config8(ctrl.d0f0, 0x4f, 0x01); + + w83697hf_set_clksel_48(SERIAL_DEV); + + w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + uart_init(); + console_init(); + + print_spew("In auto.c:main()\r\n"); + + enable_smbus(); + smbus_fixup(&ctrl); + + /* Halt if there was a built-in self test failure. */ + report_bist_failure(bist); + + print_debug("Enabling mainboard devices\r\n"); + enable_mainboard_devices(); + + print_debug("Enable F-ROM Shadow RAM\r\n"); + enable_shadow_ram(); + + /* setup cpu */ + print_debug("Setup CPU Interface\r\n"); + c3_cpu_setup(ctrl.d0f2); + + + ddr_ram_setup(); + + if (bist == 0) { + print_debug("doing early_mtrr\r\n"); + early_mtrr_init(); + } + + //ram_check(0, 640 * 1024); + + print_spew("Leaving auto.c:main()\r\n"); +} |