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author | Ronald G. Minnich <rminnich@gmail.com> | 2003-09-26 04:45:52 +0000 |
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committer | Ronald G. Minnich <rminnich@gmail.com> | 2003-09-26 04:45:52 +0000 |
commit | c817926a6bd4195cff6b6a0d8fa35b8637cee1b8 (patch) | |
tree | 0e359b22069293ab81af97c81c4e36ed083c2caa /src/mainboard/via/epia/auto.c | |
parent | 10941401e8c040ade7456b0f49ab21c6306791fd (diff) | |
download | coreboot-c817926a6bd4195cff6b6a0d8fa35b8637cee1b8.tar.xz |
via epia; also yh lu tyan.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1138 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/via/epia/auto.c')
-rw-r--r-- | src/mainboard/via/epia/auto.c | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/src/mainboard/via/epia/auto.c b/src/mainboard/via/epia/auto.c new file mode 100644 index 0000000000..5b8aa0bbdd --- /dev/null +++ b/src/mainboard/via/epia/auto.c @@ -0,0 +1,89 @@ +#define ASSEMBLY 1 + + +#include <stdint.h> +#include <device/pci_def.h> +#include <cpu/p6/apic.h> +#include <arch/io.h> +#include <device/pnp.h> +#include <arch/romcc_io.h> +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "ram/ramtest.c" +#include "northbridge/via/vt8601/raminit.h" +void udelay(int usecs) { + int i; + for(i = 0; i < usecs; i++) + outb(0x80, 0x80); +} + +#include "lib/delay.c" +#include "cpu/p6/boot_cpu.c" +#include "debug.c" + +#include "southbridge/via/vt8231/vt8231_early_smbus.c" +#define SIO_BASE 0x2e +#define MAXIMUM_CONSOLE_LOGLEVEL 9 +#define DEFAULT_CONSOLE_LOGLEVEL 9 + +static void memreset_setup(void) +{ +} + +/* +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} +*/ +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + + + +#include "northbridge/via/vt8601/raminit.c" +#include "sdram/generic_sdram.c" + +static void main(void) +{ + struct mem_controller cpu[1]; + // init_timer(); + + uart_init(); + console_init(); + + enable_smbus(); + memreset_setup(); + sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); + + + /* Check all of memory */ +#if 0 + msr_t msr; + msr = rdmsr(TOP_MEM); + print_debug("TOP_MEM: "); + print_debug_hex32(msr.hi); + print_debug_hex32(msr.lo); + print_debug("\r\n"); +#endif +#if 0 + ram_check(0x00000000, msr.lo); +#endif +#if 0 + static const struct { + unsigned long lo, hi; + } check_addrs[] = { + /* Check 16MB of memory @ 0*/ + { 0x00000000, 0x01000000 }, +#if TOTAL_CPUS > 1 + /* Check 16MB of memory @ 2GB */ + { 0x80000000, 0x81000000 }, +#endif + }; + int i; + for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) { + ram_check(check_addrs[i].lo, check_addrs[i].hi); + } +#endif +} |