newconfig is no more.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

2 files changed, 0 insertions, 299 deletions

diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb
deleted file mode 100644
index c75c21e060..0000000000
--- a/src/mainboard/via/epia/Config.lb
+++ /dev/null
@@ -1,156 +0,0 @@
-## CONFIG_XIP_ROM_SIZE must be a power of 2.
-default CONFIG_XIP_ROM_SIZE = 64 * 1024
-include /config/nofailovercalculation.lb
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if CONFIG_GENERATE_PIRQ_TABLE object irq_tables.o end
-
-##
-## Romcc output
-##
-makerule ./failover.E
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc" 
-	action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./failover.inc
-	depends "$(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c ../romcc"
-	action "../romcc    -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/../../../arch/i386/lib/failover.c -o $@"
-end
-
-makerule ./auto.E 
-	depends	"$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" 
-	action	"../romcc -E -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc 
-	depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc"
-	action	"../romcc    -mcpu=c3 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit coreboot entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where coreboot is entered)
-##
-if CONFIG_USE_FALLBACK_IMAGE 
-	mainboardinit cpu/x86/16bit/reset16.inc 
-	ldscript /cpu/x86/16bit/reset16.lds 
-else
-	mainboardinit cpu/x86/32bit/reset32.inc 
-	ldscript /cpu/x86/32bit/reset32.lds 
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of coreboot startup 
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if CONFIG_USE_FALLBACK_IMAGE
-	ldscript /arch/i386/lib/failover.lds 
-	mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu_enable.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/mmx_disable.inc
-
-##
-## Include the secondary Configuration files 
-##
-dir /pc80
-config chip.h
-
-chip northbridge/via/vt8601
-	device pci_domain 0 on
-    		device pci 0.0 on end			# Northbridge
-#		device pci 0.1 on			# AGP bridge
-		#	device pci 0.0 on end		# Integrated VGA
-#		end
-		chip southbridge/via/vt8231
-			register "enable_native_ide" = "0"
-			register "enable_com_ports" = "1"
-			register "enable_keyboard" = "0"
-			device pci 11.0 on              # Southbrdge
-				chip superio/winbond/w83627hf
-					device pnp 2e.0 on      #  Floppy
-					   io 0x60 = 0x3f0
-					  irq 0x70 = 6
-					  drq 0x74 = 2
-					end
-					device pnp 2e.1 off     #  Parallel Port
-					   io 0x60 = 0x378
-					  irq 0x70 = 7
-					end
-					device pnp 2e.2 on      #  Com1
-					   io 0x60 = 0x3f8
-					  irq 0x70 = 4
-					end
-					device pnp 2e.3 off     #  Com2
-					   io 0x60 = 0x2f8
-					  irq 0x70 = 3
-					end
-					device pnp 2e.5 on      #  Keyboard
-					   io 0x60 = 0x60
-					   io 0x62 = 0x64
-					  irq 0x70 = 1
-					  irq 0x72 = 12
-	      				end
-				register "com1" = "{CONFIG_TTYS0_BAUD}"
-				end
-				device pnp 2e.6 off end 	#  CIR
-				device pnp 2e.7 off end 	#  GAME_MIDI_GIPO1
-				device pnp 2e.8 off end		#  GPIO2
-				device pnp 2e.9 off end 	#  GPIO3
-				device pnp 2e.a off end		#  ACPI
-				device pnp 2e.b on		#  HW Monitor
-					io 0x60 = 0x290
-				end
-			end
-			device pci 11.1 on  end		# Ide
-			device pci 11.2 off end		# Usb port 0-1
-			device pci 11.3 off end		# Usb port 2-3
-			device pci 11.4 off end		# ACPI
-			device pci 11.5 off end		# AC97 Audio
-			device pci 11.6 on  end		# AC97 Modem
-          		device pci 12.0 on  end		# Ethernet
-        	end
-	end
-
-        device apic_cluster 0 on
-                chip cpu/via/model_c3
-                        device apic 0 on end
-                end
-        end
-end
diff --git a/src/mainboard/via/epia/Options.lb b/src/mainboard/via/epia/Options.lb
deleted file mode 100644
index 466ffcc382..0000000000
--- a/src/mainboard/via/epia/Options.lb
+++ /dev/null
@@ -1,143 +0,0 @@
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_CONSOLE_SERIAL8250
-uses CONFIG_TTYS0_BAUD
-uses CONFIG_TTYS0_BASE
-uses CONFIG_TTYS0_LCS
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_GENERATE_PIRQ_TABLE
-uses CONFIG_USE_FALLBACK_IMAGE
-uses CONFIG_HAVE_FALLBACK_BOOT
-uses CONFIG_HAVE_HARD_RESET
-uses CONFIG_UDELAY_IO
-uses CONFIG_UDELAY_TSC
-uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
-uses CONFIG_HAVE_OPTION_TABLE
-uses CONFIG_USE_OPTION_TABLE
-uses CONFIG_ROM_PAYLOAD
-uses CONFIG_IRQ_SLOT_COUNT
-uses CONFIG_MAINBOARD
-uses CONFIG_MAINBOARD_VENDOR
-uses CONFIG_MAINBOARD_PART_NUMBER
-uses COREBOOT_EXTRA_VERSION
-uses CONFIG_ARCH
-uses CONFIG_FALLBACK_SIZE
-uses CONFIG_STACK_SIZE
-uses CONFIG_HEAP_SIZE
-uses CONFIG_ROM_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_IMAGE_SIZE
-uses CONFIG_ROM_SECTION_SIZE
-uses CONFIG_ROM_SECTION_OFFSET
-uses CONFIG_COMPRESSED_PAYLOAD_LZMA
-uses CONFIG_PRECOMPRESSED_PAYLOAD
-uses CONFIG_ROMBASE
-uses CONFIG_RAMBASE
-uses CONFIG_XIP_ROM_SIZE
-uses CONFIG_XIP_ROM_BASE
-uses CONFIG_GENERATE_MP_TABLE
-uses CONFIG_CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses CONFIG_OBJCOPY
-
-# logging
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-
-# logging
-uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-
-uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-
-default CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID = 0x1019
-
-default CONFIG_CONSOLE_SERIAL8250=1
-## Select the serial console baud rate
-default CONFIG_TTYS0_BAUD=115200
-
-# Select the serial console base port
-default CONFIG_TTYS0_BASE=0x3f8
-                                                                                
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default CONFIG_TTYS0_LCS=0x3
-
-## CONFIG_ROM_SIZE is the size of boot ROM that this board will use.
-default CONFIG_ROM_SIZE  = 256*1024
-
-###
-### Build options
-###
-
-##
-## Build code for the fallback boot
-##
-default CONFIG_HAVE_FALLBACK_BOOT=1
-
-##
-## no MP table
-##
-default CONFIG_GENERATE_MP_TABLE=0
-
-##
-## Build code to reset the motherboard from coreboot
-##
-default CONFIG_HAVE_HARD_RESET=0
-
-##
-## use io based udelay function
-## disable IO and enable TSC on Nehemiah boards
-##
-default CONFIG_UDELAY_IO=1
-default CONFIG_UDELAY_TSC=0
-default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=0
-
-##
-## Build code to export a programmable irq routing table
-##
-default CONFIG_GENERATE_PIRQ_TABLE=1
-default CONFIG_IRQ_SLOT_COUNT=5
-#object irq_tables.o
-
-##
-## Build code to export a CMOS option table
-##
-default CONFIG_HAVE_OPTION_TABLE=1
-
-###
-### coreboot layout values
-###
-
-## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
-default CONFIG_ROM_IMAGE_SIZE = 65536
-default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE
-
-##
-## Use a small 8K stack
-##
-default CONFIG_STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default CONFIG_HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
-default CONFIG_USE_OPTION_TABLE = 0
-
-default CONFIG_RAMBASE = 0x00004000
-
-default CONFIG_ROM_PAYLOAD     = 1
-
-##
-## The default compiler
-##
-default CONFIG_CROSS_COMPILE=""
-default CC="$(CONFIG_CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-end