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author | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:15:48 +0000 |
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committer | arch import user (historical) <svn@openbios.org> | 2005-07-06 17:15:48 +0000 |
commit | acfaeceffd8b97715905f074a76e0d12f0d83889 (patch) | |
tree | 4a7c4b12a2dff67225cc39e0f47c4d0eac84979b /src/mainboard/via/epia | |
parent | 9c3f37cb5f741d7b2ba7852a16ffb82ee40968e9 (diff) | |
download | coreboot-acfaeceffd8b97715905f074a76e0d12f0d83889.tar.xz |
Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-36
Creator: Li-Ta Lo <ollie@lanl.gov>
emulator update
Correction to the reduce emulator from Paulo
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1952 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/via/epia')
-rw-r--r-- | src/mainboard/via/epia/Config.lb | 117 | ||||
-rw-r--r-- | src/mainboard/via/epia/Options.lb | 19 | ||||
-rw-r--r-- | src/mainboard/via/epia/auto.c | 24 |
3 files changed, 84 insertions, 76 deletions
diff --git a/src/mainboard/via/epia/Config.lb b/src/mainboard/via/epia/Config.lb index 448d86fb09..96c543a1ec 100644 --- a/src/mainboard/via/epia/Config.lb +++ b/src/mainboard/via/epia/Config.lb @@ -125,61 +125,64 @@ dir /pc80 config chip.h chip northbridge/via/vt8601 - device pci_domain 0 on - device pci 0.0 on - chip southbridge/via/vt8231 - register "enable_usb" = "0" - register "enable_native_ide" = "0" - register "enable_com_ports" = "1" - register "enable_keyboard" = "0" - register "enable_nvram" = "1" - device pci 11.0 on # Southbridge - device pci 11.1 on end # Ide - device pci 11.2 off end # Usb - device pci 11.3 off end # Usb - device pci 11.4 off end # ACPI - device pci 11.5 off end # Audio - device pci 11.6 on # Com - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off end # CIR - device pnp 2e.7 off end # GAME_MIDI_GIPO1 - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - end - register "com1" = "{1}" - end - end - device pci 12.0 on end # Ethernet - end - end - end - end - chip cpu/via/model_centaur - end + device pci_domain 0 on + device pci 0.0 on end # Northbridge + device pci 0.1 on # AGP bridge + # chip drivers/pci/onboard # Integrated VGA + # device pci 0.0 on end + # register "rom_adress" = "0xfff80000" + # end + end + chip southbridge/via/vt8231 + register "enable_native_ide" = "0" + register "enable_com_ports" = "1" + register "enable_keyboard" = "0" + device pci 11.0 on # Southbrdge + chip superio/winbond/w83627hf + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + register "com1" = "{1}" + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GAME_MIDI_GIPO1 + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # HW Monitor + io 0x60 = 0x290 + end + end + device pci 11.1 on end # Ide + device pci 11.2 off end # Usb port 0-1 + device pci 11.3 off end # Usb port 2-3 + device pci 11.4 off end # ACPI + device pci 11.5 off end # AC97 Audio + device pci 11.6 on end # AC97 Modem + device pci 12.0 on end # Ethernet + end + end + + chip cpu/via/model_centaur + end end diff --git a/src/mainboard/via/epia/Options.lb b/src/mainboard/via/epia/Options.lb index d8d3490dd0..259acfbc24 100644 --- a/src/mainboard/via/epia/Options.lb +++ b/src/mainboard/via/epia/Options.lb @@ -1,3 +1,10 @@ +uses MAXIMUM_CONSOLE_LOGLEVEL +uses DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_CONSOLE_SERIAL8250 +uses TTYS0_BAUD +uses TTYS0_BASE +uses TTYS0_LCS +uses CONFIG_CHIP_NAME uses HAVE_MP_TABLE uses HAVE_PIRQ_TABLE uses USE_FALLBACK_IMAGE @@ -40,6 +47,18 @@ uses MAXIMUM_CONSOLE_LOGLEVEL uses DEFAULT_CONSOLE_LOGLEVEL uses MAXIMUM_CONSOLE_LOGLEVEL +default CONFIG_CONSOLE_SERIAL8250=1 +## Select the serial console baud rate +default TTYS0_BAUD=19200 + +# Select the serial console base port +default TTYS0_BASE=0x3f8 + +# Select the serial protocol +# This defaults to 8 data bits, 1 stop bit, and no parity +default TTYS0_LCS=0x3 + +default CONFIG_CHIP_NAME=1 ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE = 256*1024 diff --git a/src/mainboard/via/epia/auto.c b/src/mainboard/via/epia/auto.c index 6c8ea903ee..9e12f52a7c 100644 --- a/src/mainboard/via/epia/auto.c +++ b/src/mainboard/via/epia/auto.c @@ -2,9 +2,6 @@ #include <stdint.h> #include <device/pci_def.h> -#if 0 -#include <cpu/x86/lapic.h> -#endif #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> @@ -21,7 +18,7 @@ void udelay(int usecs) { int i; - for(i = 0; i < usecs; i++) + for (i = 0; i < usecs; i++) outb(i&0xff, 0x80); } @@ -30,18 +27,8 @@ void udelay(int usecs) #include "debug.c" #include "southbridge/via/vt8231/vt8231_early_smbus.c" - - #include "southbridge/via/vt8231/vt8231_early_serial.c" -static void memreset_setup(void) -{ -} -/* - static void memreset(int controllers, const struct mem_controller *ctrl) - { - } -*/ static inline int spd_read_byte(unsigned device, unsigned address) { unsigned char c; @@ -49,8 +36,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) return c; } - - #include "northbridge/via/vt8601/raminit.c" /* #include "sdram/generic_sdram.c" @@ -66,6 +51,7 @@ static void enable_mainboard_devices(void) if (dev == PCI_DEV_INVALID) { die("Southbridge not found!!!\n"); } + pci_write_config8(dev, 0x50, 7); pci_write_config8(dev, 0x51, 0xff); #if 0 @@ -87,9 +73,9 @@ static void enable_mainboard_devices(void) static void enable_shadow_ram(void) { - device_t dev = 0; /* no need to look up 0:0.0 */ + device_t dev = 0; unsigned char shadowreg; - /* dev 0 for southbridge */ + shadowreg = pci_read_config8(dev, 0x63); /* 0xf0000-0xfffff */ shadowreg |= 0x30; @@ -113,8 +99,8 @@ static void main(unsigned long bist) enable_mainboard_devices(); enable_smbus(); enable_shadow_ram(); + /* - memreset_setup(); this is way more generic than we need. sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu); */ |